As semiconductor fabrication has advanced inexorably to the beat of Moore’s drum, low power VLSI circuits containing large numbers of signal processing channels have become increasingly available. Concurrently, solid state detector fabrication, following the same parade, has produced increasingly larger and denser arrays of segmented detectors. The marriage of these two technologies in a functioning high channel count high performance detector depends on one more element: a suitable interconnection technology.
That technology must meet some rigorous requirements. The interconnections must be physically small, to accommodate closely spaced detectors while minimizing the non-active detector area sacrificed to interconnections. The interconnections must be inexpensive, because the exponential growth in the number of detector channels cannot, in the practical world, be accompanied by a similar exponential growth in cost. The interconnections must facilitate high speed signal transmission, to maintain system speed. They must be reliable, with high connection yield in large arrays. They must be rugged, to withstand harsh environments such as in spacecraft. They must be of materials compatible with the detectors and not incompatible with the detectees. Finally, the interconnection process must be gentle, because some high performance detector materials are soft, brittle, or intolerant of elevated temperatures.
Flip chip interconnection is a natural solution for this difficult task. It is the smallest interconnection method, wasting the least possible area. By eliminating the inductance of bond wires, flip chip offers the highest speed interconnection. Flip chip is inherently rugged, with no bond wires flailing about under vibration. Flip chip allows, no, encourages area, rather than peripheral, interconnection. Flip chip is potentially the lowest cost interconnection, especially in large arrays. However, there are many varieties of flip chip interconnection, and not all are equally well suited to detector arrays.
Solder bump flip chip in its various mutations has the longest production history and the most impressive reliability data. However, solder has clear disadvantages in this application. Conventional solder bumps cannot offer the required fine spacing, because of the bridging proclivities, the urge to merge, of molten closely spaced blobs of solder. Solder processing temperatures are too high for thermally intolerant detectors. Lead is an excellent shielding material, absorbing x-rays and screening out particles, while contributing a few alpha particle emissions of its own, making it not a good neighbor in most X-ray and particle detectors.
Indium bump flip chip has a long and checkered history in detector applications. Indium is commonly used, but many of the users swear at it, rather than swear by it. Indium bumping offers the worst of both worlds: high cost and high temperature processing. Sensitive detector surfaces such as Cadmium Zinc Telluride (CdZnTe) may be damaged by indium bumping, and processing temperatures are higher than the 125 C maximum desired for these materials.
The stud bump flip chip process also has the advantage of being chip-based, rather than wafer based, so that signal processors may be obtained, bumped, and used in only the needed quantities, a considerable cost saving.1 The stud bump assembly procedure also allows testing for “known good die” in the actual circuit, the best place to seek such animals, and easily replacing “found bad die” if needed.
X-Ray Spectrographic Detector Array
Seller reported on the construction and performance of a 256 pixel high energy X-ray silicon 16×16 detector array fabricated with gold stud bump adhesive flip chip.2 The array comprised a silicon detector chip with 256 detectors individually interconnected by stud gold bumps to the signal processor chip.
The processor chip has 256 aluminum bond pads measuring 50 by 115 microns. Connection was through a gold stud bump on each of these pads, using 100 micron diameter gold-palladium wire in a Hughes 2460 wire bonder. Figure 1 shows a portion of the stud bump array on the electronics chip. Note that the stud bumps fit well within the pad boundaries. The wire tails show height variations that are well within the acceptable range.
The detector chips had larger pads than the processor chip, more than adequate for precision stenciling of the conductive mounting adhesive to connect each pixel of the gold stud bumped chip to the processor. However, the detector chips are fabricated with the aluminum metallization typical of semiconductor processing. While the gold stud bump penetrates the aluminum oxide on the electronics chip, it cannot, without application of considerable heat and pressure, also penetrate the aluminum oxide on the detector chip pads. These pads instead were first treated with an under-bump remetalization, applied by Pac Tech.
The remetalization was by the zincate process described elsewhere in the literature.3 A layer of zinc seed crystals replace the aluminum oxide, and serve as a base for plated nickel. A flash of electroless gold provides the frosting for this nickel cake. The gold provides a suitably conductive surface for stenciling the conductive mounting adhesive to the gold stud bumps. The stud bumps were aligned to the detector pads and joined in an SEC 810 Flip Chip bonder. The adhesive was Alpha Metals Polysolder, and the underfill Alpha EL-18.
Note that the adhesive is uncured on assembly, and does not comprise part of the bumping process. The conductive adhesive layer is component attach for the gold stud bump. Depending on the assembly method used, the electrical contact may be gold to gold, with little or no adhesive remaining between the stud bump and substrate.
Protein Crystallography Detector Array
A second detector array extended this process to smaller dimensions. The 16×16 pixel detector array is a scaling up of an earlier 8×8 array.4
Figure 2 shows a portion of the bond pads for the array. In this case, the aluminum pads are smaller than for the array described above. Pad size is 50 microns square, and the pad spacing is asymmetric, 150 microns by 105 microns.
Figure 3 shows gold stud bumps placed on these pads. As shown, the bump extends beyond the pad opening, onto the glassivation. This has not caused any electrical problems. However, the closer spacing of pads caused some interference by the bonder capillary with the first stud bump when placing the adjacent stud bump. A special capillary was required to place satisfactory stud bumps.
Figure 4 shows a portion of the resulting stud bump array.
There are a growing number of applications that would benefit from multi-channel close spaced detector arrays. In addition to those described above, we have found opportunities in nuclear medicine, medical imaging, and high energy astrophysics.
In astrophysics, NASA has stated needs for double sided fine pitch (100 micron to 0.5mm) silicon strip x-ray and gamma-ray detectors, high resolution germanium strip detectors, and Cadmium Zinc Telluride detector arrays with 500 micron pixel sizes. Applications include focal plane pixel arrays for hard x-ray telescopes, strip detectors for hard x-ray coded aperture telescopes, and strip detectors for particle trackers.
The key spacing limitations on the stud bump arrays described above naturally divide into those of fabricating smaller bumps on closer pitches, and those of dispensing adhesive onto these smaller bumps. The present limits were set by wire bonding and stenciling capabilities.
The bumps described above were placed with the Hughes 2460, a machine several generations older than current bonders. The 105 micron bump pitch is close to the limits of this machine, but current machines can achieve finer pitches. Newer wire bonders have demonstrated ball bond pitches below 50 microns . This has the potential to greatly increase array density.
Similarly, adhesive dispensing by stencil appears to be approaching its limit in the 50 micron region. However, higher density may be obtained with adhesive dispensed by the dipping process.5 In this method, a thin layer of adhesive is doctor bladed onto a flat surface, and the stud bumps are dipped into it. Dipped adhesive coats only the bump itself, not extending outwards onto the pad.
Flip chip with gold stud bumps and conductive adhesive has been shown to be a practical interconnection technique for detector arrays. It offers advantages over both Indium bump and solder bump flip chip interconnection, especially with temperature-limited detector materials. The approach is capable of extension to the finer detector spacing and larger arrays required by a growing variety of applications.
This tutorial is a revision of “Flip Chip Interconnection of Detector Arrays, ” Proceedings of IPS/SMTA Electronics Assembly Expo, October, 1998, pp. S18-3-1 to S18-3-4.
 G. Riley, “Bump, Dip, Flip: Single Chip,” Proc. Surface Mount International Conference, Sept. 1997, pp. 535-541.
 P. Seller et al., “Silicon Pixel Detector for X-Ray Spectroscopy,” EUV, X-Ray, and Gamma Ray Instrumentation for Astronomy, SPIE Vol 3445, July 1998.
 G. Riley, “Adhesive Flip Chip Assembly Using Plated Bump Chips,” Proc. IEEE International Electronics Manufacturing Technology Symposium, Oct. 1997, pp. 313-318.
 P. Datte et al., “A Prototype 8×8 Pixel Array X-Ray Detector for Protein Crystallography,” Nuclear Instruments and Method in Physics Research, A 396, 1997.
 G. Riley, “Flip Chip Interconnection: Dream or Nightmare?” Proceedings of the Third Workshop on Electronics for LHC Experiments, CERN/LHCC/98-60, pp. 107-111.