James E. Clayton
An extended abstract of a paper to be presented at IMAPS 2003, November 18, 2003
High-density flip chip assembly combined with low temperature processing is emerging as a critical path for the successful development of many sensor and imaging devices. Many of these sensors employ fine pitch pixel array patterns requiring more than 1,000 interconnections, and limited to processing temperatures below 100 C.
A polymer adhesive approach, combining gold stud bumped devices with stencil printed conductive epoxy, offers fine pitch and low temperature curing. Chips with pin counts as high as 8,000 I/O have been assembled with this method.
Flip Chip Assembly with Conductive Adhesives
Silver-filled conductive epoxies have been around for over thirty years, but in the United States have been bypassed for solder in most flip chip applications. This differs from Japan and Europe, where conductive epoxies have received far more interest and study, and are used in high volume assembly of inexpensive mobile products.
In Japan, flip chip assembly with conductive epoxies is almost exclusively used in combination with gold stud bumped chips. The tips of the gold stud bumps are first dipped into a thin layer of the epoxy that has been spread across the surface of a rotating platter using an adjustable doctor blade. The conductive adhesive wets the substrate pads when the dipped chip is aligned and placed onto the substrate. Regulating the amount of epoxy material transferred onto the gold stud bumps is critical for ensuring high assembly yields, since electrical shorts may develop between adjacent bumps, either from bridging during the dipping process, or from epoxy spreading during chip placement.
Stencil Printed Polymer Bumping
An alternative adhesive assembly process is stencil printing the conductive adhesive directly either onto the device or substrate pads, and then aligning and placing the gold stud bumps formed on the other component into the stenciled adhesive before curing. Since the amount of epoxy can be more precisely controlled than in dipping, shorting of adjacent bumps is less likely In addition, the stenciled adhesive shape provides a robust contact between the bump and the substrate pad. As shown in Figure 1, stencil printed polymer bumps resemble a rounded volcano.
Figure 1. Stencil printed, conductive epoxy bump ( approximately 150µm diameter).
The stencil printing method is also more tolerant of stud bump height variations than the dip-transfer method, since the chip’s gold stud bumps typically penetrate the full thickness of the printed epoxy bumps until they touch the underlying pads.
CdZnTe Detector Assembly
Figure 2 shows a CdZnTe (CZT) detector populated with an array of over 1056 polymer bumps. These bumps are spaced on a 498µm array, and range from 130 to140µm in diameter, and 25 to 27µm in height. This detector was designed at Caltech for the High-Energy Focusing Telescope (HEFT), scheduled for a balloon-launched experiment sometime in 2004. 
Figure 2. A portion of a 24X44 CdZnTe pixel-array with conductive epoxy bumps spaced 498µm apart. The bumps are purposely offset from the center-point of each pixel.
The detector is attached to a custom low-noise analog very-large-scale-integration (VLSI) readout chip that functions as a sensitive preamplifier for hard x-ray imaging. The VLSI chip has an identical array of gold stud bumps that are aligned and mated to the epoxy bumps on the CZT detector.
Minimizing detector noise required that no underfill epoxy be used for this assembly. Mechanical integrity at near-zero temperatures depends on the large number of epoxy bonds, along with an approximate match in the thermal expansion coefficient (CTE) of the materials.
This assembly also required that none of the bump epoxy come into contact with the pads on the VLSI chip. The stencil printing technique was controlled to deposit a very precise mass and a uniform shape of epoxy on the CZT pads. As shown in Figure 3, this limited the adhesive depth to only half of the stud bump height of 44 micrometers.
Figure 3. SEM image of a gold stud bump centered within and connecting to a silver filled, conductive epoxy bump. Note that the epoxy does not reach the surface of the VLSI chip.
As gold stud bump diameters have decreased, and conductive materials and application techniques have improved, this assembly technology has become well suited for very fine pitch, high pin count applications. The techniques described in this article may also be adapted for future optical chip-to-chip interconnect using fiber optic columns bonded with stencil printed, optically translucent, epoxy bumps.
1. C. M. Hubert Chen, Walter R. Cook, Fiona A. Harrison, Jiao Y. Ylin and Peter H. Mao, “Characterization of the HEFT CdZnTe Pixel Detectors”, Hard X-Ray and Gamma-Ray Detector Physics V, Proc. of SPIE, Vol 5198, in print.
For More Information
A complete version of this six-page paper will appear in the IMAPS International Symposium 2003 Proceedings.
The author may be contacted at:
Polymer Assembly Technology, Inc, 14 Fortune Drive, Billerica, MA 01821
Phone: 978-667-0071, Fax: 978-667-4784