Most MEMS cavity packages are hermetically sealed by either glass frit seals or anodic bonding. However, neither technique supports the smaller feature size, CMOS-compatible packaging required for advanced MEMS and 3D devices.
Eutectic wafer-to-wafer bonding solves these problems with high precision CMOS-compatible seals for advanced MEMS and 3D packaging.
Glass Frit Bonding
Glass frit seals have been the workhorse for MEMS packaging because they tolerate surface roughness and particles while providing a low-cost hermetic seal. Frit seals are created by heating glass paste on a cover wafer to create sealing rings. Bringing the cover wafer and MEMS wafer together under heat and pressure forms the glass seal. The resulting seals are typically 70 µm to 200 µm wide, and equally thick (FIG 1).
They cannot be made smaller because the relatively low hermeticity of glass compared with metal requires thick layers. In addition, ionic contamination makes glass frit seals incompatible with CMOS processing.
Figure 1. Cutaway view of a glass frit sealed wafer-level chip-scale package with a seal width of about 250 µm. (Courtesy IMEC)
Anodic bonding takes place when silicon wafers and sodium-containing glass are subjected to heat, high pressure, and a direct-current electric potential of 200 to 1,500 volts. The electric potential causes mobile ions to move away from the junction though the heat-softened glass, with silicon ions moving towards the junction to replace them. The resulting permanent electrostatic field at the junction holds the glass and silicon together.
Anodic bonds are strong and hermetic, but forming them requires particle-free surfaces with roughness less than 20 nm. Ionic contamination makes anodic bonding incompatible with CMOS processing.
Certain pairs of elements, determined by their crystalline structure, will undergo a eutectic transition at some specific composition ratio and temperature. A eutectic transition occurs at a critical temperature where two metals in proper proportions pass directly from solid to liquid (or vice-versa) phases without passing through an intermediate solid plus liquid phase. Figure 2 shows the gold-tin phase diagram.
Figure 2. Gold-tin phase diagram, showing the eutectic point at 280C, 20 weight % tin. (Courtesy of Advanced Packaging) Common eutectic alloys for packaging applications include Au-In, Cu-Sn, and Au-Sn, with transition temperatures ranging from 156°C for Au-In to 280°C for Au-Sn. The metals can be deposited over adhesion layers in thin, well-controlled patterns. The deposits may be as pure materials which will interdiffuse to a eutectic combination, or as a binary alloy at the eutectic composition.
Eutectic bonding requires careful control of both temperature and pressure during sealing. Tool parallelism and uniform temperatures and pressures must be maintained throughout. Processing time is relatively short. The resulting joint is strong and rigid, and the edge of wafer is sealed, preventing fluid penetration during later processing.
The hermeticity of metal is orders of magnitude greater than glass, allowing a eutectic metal seal as small as 1 µm thick and 10 µm wide to provide hermeticity superior to the much thicker glass frit seals. The smaller eutectic seal can allow hundreds more die per wafer than a frit seal. It also allows scalability as device feature sizes shrink.
As with glass frit seals, the liquid layer formed during eutectic sealing makes it tolerant of particles, surface roughness, and device topography. Eutectic processes are fully compatible with CMOS processing, and post-bond alignments may be less than 2 µm.
Eutectic metal wafer seals have major advantages over older techniques as described above, and support the growing needs for high-precision CMOS-compatible sealing for both MEMS devices and for 3D packaging.
FOR MORE INFORMATION
“Precision Wafer-to-Wafer Packaging using Eutectic Metal Bonding,” Shari Farrens, Ph.D., SUSS Microtec, SMTA Pan Pacific Symposium, Hawaii, January 24, 2008.
“Enabling next-generation MEMS devices with Metal Eutectic Bonding” Keith Cooper, SUSS Microtec, Small Times, September – October issue, 2008.
“Wafer Level Packaging: Balancing Device Requirements and Material Properties,” Shari Farrens, Ph.D. and Mr. Sumant Sood, SUSS Microtec, IMAPS 41st International Symposium on Microelectronics, Providence, Rhode Island, November 2, 2008.