Summarized from: Flip Chip Assembly Method Employing Differential Heating/Cooling for Large Dies with Coreless Substrates
Presented at Electronic Components and Technology Conference 2013, IEEE 63rd. Full paper available at: IEEE Xplore
Katsuyuki Sakuma, Edmund Blackshear, Krishna Tunga, Chenzhou Lian, Shidong Li, Marcus Interrante, Oswald Mantilla (IBM Microelectronics Division,
Hopewell Junction, NY) and Jae-Woong Nah (IBM T. J. Watson Research Center, Yorktown, NY)
IBM’s research of a differential heating/cooling chip join process that was developed for coreless flip chip packaging — to minimize warpage change of coreless substrates during the bonding process.
As the performance of semiconductor systems improves, there is an increasing demand for high speed data transmission and lower power dissipation. To achieve performance targets, low-k dielectric materials are used in the back-end-of-line (BEOL). However, these materials intrinsically have a lower modulus and hardness, and weaker adhesion compared to the oxide layers present within the BEOL layers. This creates a potential for various mechanical failures during the flip chip assembly process, such as delamination and cracks in low-k layers.
From a packaging substrate point of view, one solution for high speed applications is to reduce or remove the core layer thickness. By doing this, interconnection becomes shorter and the resistance and inductance of the through-holes within the rigid core layer can be reduced or eliminated. Consequently, superior electrical performance and cost reduction become possible.
A schematic cross-section of conventional packaging structure and coreless packaging structure is shown below.
However, a large coefficient of thermal expansion (CTE) mismatch between a silicon chip and an organic substrate still exists and that induces thermal mechanical stress and strain at the interconnections. Furthermore, thermal warpage of coreless substrates is larger than that of conventional thick core substrates because there is no rigid thick core material. This leads to earlier fails in coreless packages during the bonding and assembly process, compared to conventional thick core substrates. If a conventional reflow process is adopted for assembling silicon chips on coreless substrates, the high degree of substrate warpage results in non-wetting of C4s and/or bridging between solder joints. This influence becomes more pronounced as the chip size increases and the pitch of electrical interconnection decreases, which is common for high performance application chips. Therefore, there is an increase in demand for a new chip join method to reduce coreless substrate warpage during the assembly process for flip chip packaging.
SUMMARY OF THE WORK:
A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) – related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference between the Si chip and the organic substrate during assembly provides a substantially matched thermal expansion and minimizes stress induced by coefficient of thermal expansion (CTE) mismatch. From the modeling study, it was confirmed that chip warpage, Controlled Collapse Chip Connection (C4) stresses/strains, and ULK stresses decreased significantly by differential heating/cooling chip join method, with further improvement noted as the substrate temperature was decreased during the bonding process. X-ray, scanning electron microscope (SEM) and C-mode scanning acoustic microscope (C-SAM) were used to examine the defects after flip chip assembly. Noncontact white light reflectometry was also used to measure the warpage shape of the assembled silicon chip and the organic substrate. Observation under C-SAM indicated that fractures in the ULK layers were dramatically reduced by the differential heating/cooling chip joining process compared to the conventional reflow process. Non-destructive X-ray images indicated there were no solder bridging in any area of the chip interconnects. The experimental results showed that the differential heating/cooling chip join process can effectively reduce fractures in the ULK layers and prevent C4 bump bridging in a large die package with low-K dielectric constant device integration and high Ag content solder bumps.
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd