Converting a “conventional” wirebond die into a flip chip die generally requires that a series of back end steps are performed on a full sized wafer. This normally requires a set of 4 masks on large glass plates (10 inch for 200 mm wafers and 14-15 inches for 300 mm wafers.) These masks include the following:
VIA-1 – used to expose the original die pads after a polyamide layer has been spun over the wafer.
RDL – (redistribution layer) used to define metal traces from the original die pads to the new locations for the bumps. Note that the RDL metal is applied initially by sputtering and then is plated up to the desired thickness.
VIA-2 used to create openings in the dielectric over the RDL metal where the bumps will go.
UBM – (under bump metal) used to define and plate up metal connecting the RDL layer to the bump.
SOLDER – used to produce a screen or stencil through which solder is applied to the under bump metal. The round solder bumps will adhere to this solder. You don’t need an expensive glass mask for this — a film mask will be sufficient.
The Unit Cell Design
The unit cell can be designed with various software tools: IC Layout tools such as Cadence Virtuoso or Tanner’s LEDIT, Package Design tools such as Cadence APD/SIP or even AutoCAD. The designs are relatively straightforward – normally starting with the original chip’s passivation layer to identify the die pad openings. Shown below are the 4 layers (UBM and SOLDER MASK are identical) that I drew for this example.
The data format for the RDL mask set is normally GDSII stream format. This can be accepted by the photo mask shop and converted into the format that drives a variety of image writers designed for large glass plates.
Wafer and Die Size
In this example we are working with:
a) a 200 mm diameter wafer
b) an exclusion zone of 2.5 mm at all edges of the wafer
c) a die of 3000 x 3000 um with a street width of 25 um
You can see a simple drawing of where we are starting below:
Stepping the RDL Cell to Match Die Already on the Wafer
Since a wafer has already been built, we need to array our unit RDL cell to exactly match the array of die on the wafer. This requires both a) that we use the correct step size and b) that we shift or offset our RDL array so that it matches the how the original die was stepped.
Normally die placement information is provided by the fab that built the wafer. However it may be provided in a way that requires some analysis or massaging to be useful to the flip chip mask designer. Most fabs use a reticle and you may get the reticle flash locations. You will then need to know more about the die’s location on the reticle in order to find the center and extents of the array.
The fab should also supply some coordinates (with respect to the center of the wafer) that tell you where test devices are located and where a wafer ID and fiducials are located. We will need this information to knockout regions of our Flip Chip masks so that these locations can be accessed or viewed.
Getting the Array Aligned
Generally there is no problem getting the die stepping information in terms of the X and Y stepping distance. However getting information about how the array is “centered” on the wafer is another matter. There are three options:
(a) The array is die centered
(b) The array is street centered
(c) The array is neither die nor street centered
street centered array
die centered array
If the array of die on the wafer was neither street centered nor die centered then the fab will have to provide you a diagram of the offset of the center of the array with respect to the center of the wafer. It is very important to get this right and it may be worthwhile, prior to making a glass mask, to create a film mask which is very cheap showing the array outlines and cutouts and physically checking against a completed wafer.
Offset centered array
GDS-SR A Stepping program for Round Wafers
Some years ago we developed GDS-SR a specialized stepping program for round wafers. The initial user was working on MEMs circuits and his designs were small in complexity compared to an IC chip. The GDS-SR program turns out to be very useful for wafer scale masks.
To use the stepping part of the program the user specifies:
wafer diameter, margin and flat(s)
stepping values in X and Y and any offset if needed
The program steps the die out to the edge of the wafer’s margin but does not place any die that is not completely inside of the margin.
To direct GDS-SR to step our redistribution circuit, we first enter the wafer size and margin. Notice that in this case we have actually entered a diameter that is larger than our wafer.
This is to overcome GDS-SR’s behavior of not inserting a cell if any part of it crosses the edge of the boundary. Since we are going to use another program to smoothly clip the data, we need the data to extend out past the desired clipping boundary.
After loading our unit cell we then set the stepping parameters. Because we drew 1/2 of the street as part of the cell, we will step to exactly the extents of the cell.
If we needed to offset our array to match the die already on the wafer we would enter the offset distance into the field marked SREF Offset.
To produce an array of the unit cell all we have to do is to select: Export GDSII and save the new file. We’ll call it array_all.gds.
If you’d like to examine the array just click on the link: array_all.gds 298KB
Plated Layers Need Constant Density …
Two of the masks we are preparing involve plating — the RDL mask and the UBM mask. In both cases the mask defines areas where metal will be deposited and plated up. The very first thin layer of metal is applied by sputtering — but the sputtering process builds up the metal very slowly so it is only used to put a very thin layer down. Then more metal is applied by plating over the sputtered layer.
You could say that plating is both a chemical and a physical process. It turns out the the rate of plating of any particular location depends on the density of the plating chemicals and the density of the electrical current. These are both affected by the local density of the metal being plated.
If you have abrupt changes in metal density, you will get non-uniform plating and this can adversely affect the yield of your circuits.
The bottom line is that one has to maintain the metal density over the “good” cells or you may lose them due to poor plating.
If we were to step out our RDL circuit only to the limit of the good cells on the wafer we would have metal density discontinuity along the periphery which will cause non-uniform plating.
To get better density along the wafer periphery we should instead use a smooth round clipping window as shown in the next illustration.
What we’ve done is to a) extend the array past the desired good die and b) clip smoothly to the “edge” of the wafer.
The metal on the partial die acts as a buffer between the edge of the wafer so that the good die are uniformly plated.
How do we achieve this effect?
Well, we could use a GDSII polygon editor to manually explode and edit each cell along the outer edge of the array but you are talking about editing several hundred cells.
But we’ll get the job done in seconds … not in hours … using the HExtract program.
Knocking Out Openings in Our Mask
There are several places in our array of RDL circuits where we have to open up the mask so that underlying identification and alignment targets are visible. Normally the mask designer gets a list of window locations and sizes. HExtract can automate this process also to avoid hand editing.
We have a total of 6 openings to create:
Again we will have HEXtract clip them smoothly so that the RDL and UBM layer do not suffer to much metal density variations.
HEXtract Command Line Syntax
We’ll create a simple batch file that calls HEXtract 5 times — once for each layer. However because there are so many cutouts, we will use an include file to list the cutouts.
Here is the contents of the include file, cutouts.txt
Here is an annotated command line for one mask
We’ll repeat the same command line changing the file names and layers each time. The only difference will be on the solder mask layer. For that layer we will use the additional option -drop_partial_poly.
Here is what the RDL layer looks like after knockouts generated by HExtract:
Top section of wafer
Zoomed in again
If you’d like to examine the GDSII files after the target and fid windows have been knocked out, click on the file below:
masks_bf_targets.zip GDSII Stream Zipped (4 MB)
GDSFILT – Merge Files
We will use Artwork’s GDSFILT program to merge the arrayed data with the proper FID file. While GDSFILT has a GUI, I like to use a batch file since it can be easily modified for the next similar project.
Here is the gdsfilt syntax and a short explanation that will do the merging ….
We will merge FILE_A (TOP_A) with FILE_B (TOP_B) to create file MASK (TOP).
Yes, the order of the files and structures is a bit convoluted …
Here is our batch file …. (line breaks just for clarity)
Here is a snapshot of the RDL mask with a fiducial placed in one of the knocked out regions:
Here is a snapshot of the VIA2 mask with a target placed in one of the knocked out regions:
If you wish to examine the final masks files along
with the separate files that were created for the targets
and fids you can download them from the link below:
final_mask_and_fids.zip 4 MB zipped GDSII files.
Special Solder Mask/Stencil Issues
Bumps are attached to the openings defined by the UBM mask. However because we are “slicing” the UBM geometries at the boundary, there will be many instances of a partial round opening. We do not wish to try to attach a bump to such an opening as it may come off. So when we build our solder stencil, we want to make sure that no solder paste is screened over any partial UBM opening.
We achieve this in HEXtract by using the -drop_partial_poly command line option when producing the solder mask. Below you can see an overlay of the solder bump layer and the UBM layer. Notice that there are no solder bumps (blue) over the partial UBM openings (magenta)