John H. Lau and S. W. Ricky Lee
System-on-a-Chip (SOC), System-on-a-Package (SOP), and Wafer-Level Chip-Scale Package (WLCSP), is excepted from Chapter 1, “Introduction to Microvia and WLCSP Technologies,” in the recent book “Microvias,” by John H. Lau and S.W. Ricky Lee.
While SOC, SOP, AND WLCSP are common acronyms in microelectronics packaging technology, their definitions, differences, and differing technical challenges are not commonly compared. Further chapters of this book go into more detail on these topics.
“SOC, SOP, and WLCSP”
excerpted by permission from
Chapter 1 “Introduction to Microvia and WLCSP Technologies”
in “Microvias For Low Cost, High Density Interconnects”
by John H. Lau and S. W. Ricky Lee
Copyright 2002, The McGraw-Hill Companies, Inc., New York, NY
1.2 System-on-a-Chip (SOC)
One of the 12-inch wafer semiconductor fabricator’s future integrated circuit (IC) products is system-on-a-chip (SOC), which contains diverse functions on a single, large, and complex chip. These chip design and build cycles usually are long and require multiple design passes to complete.
The advantages of SOC are performance, small system form factor, and potentially low system cost. The challenges of SOC are:
to deal with the cost of large ICs, the slowdown in the reduction of cost per transistor as a result of very low IC yields, and the very high wafer FAB costs that are estimated to be in the range of $3 to 5 billion;
to integrate the intellectual property from multiple, possibly independent sources, with attendant interoperability, integration, and liability hurdles;
to meet the mixed-signal requirements of future products, mixed technology systems, design issues, and limitation of on-chip performance that the industry faces for the first time.
1.3 System-on-a-Package (SOP)
Based on the trends in the semiconductor industry, IC packaging can look forward to solid growth in the next few years, as shown in Table 1.1. It can be seen that chip scale packages (CSPs) have the largest percentage of CAGR, followed by the ball grid array (BGA) and the direct chip attach (DCA). Although there is no way to determine the exact total revenue of IC packaging, 10 percent of the total semiconductor revenue is a reasonable guess for the total IC packaging revenue. In that case, the total revenue of IC packaging should be $32 billion by 2004.
TABLE 1.1 IC Package Forecast by Package Family
For very high-volume and simple applications, SOC is particularly appropriate. However, for mixed technologies, lower volumes, and the integration of passives, SOP is the most appropriate. SOP is an attractive alternative to SOC design complexity and uses a lower-risk approach that permits the use of mature semiconductor and packaging technologies and standard chip-to-package attach methods.
In the case of printed circuit board (PCB) design of multiple packaging technologies such as wire bonding, DCA, CSP, and BGA, it is often clear that designing and manufacturing a PCB containing all these diverse technologies can be expensive and time consuming. Moreover, in these designs, clusters of functionally related components can be identified as ideal candidates for functional subassemblies – a microprocessor and its buffer memory, and input/output (I/O) processor and interface chips.
Packaging technology has now progressed to the point where these “systems” (subsystems) can be contained on an independent package called a few-chip module (FCM). This package can be assembled and tested separately, often resulting in saving of PCB space and cost, simplification of the substrate carrier (either organic or ceramic), and lower overall packaging costs.
Electrical performance is enhanced through shorter interconnections of chip on SOP. The use of reference planes allows isolation of critical nets. Impedance/coupling levels can be controlled. Current design ground rules allow regions of very dense wiring to permit interconnection of high chip pin counts. Using glass-ceramic or organic materials offers the fastest propagation speeds and lowest line resistances.
The close physical proximity of the components mounted on SOP can minimize operating temperature deltas and permit thermal tracking, improving system performance. Use of an FCM allows designers to optimize that set of components for performance through functional subsystem testing prior to PCB assembly, allowing simplification of board test.
The compacting of several electrical functions into SOP usually leads to some thermal challenges. Unless power and airflow levels are such that no heat management is necessary, the package components will have their own unique solutions. On simple two (or three)-chip SOPs, separate heat spreaders can be attached to each chip, depending on its power level. If space permits, an advanced thermal compound can be dispensed onto each component and a full module cap can be used. The differing expansion rates of each element in the SOP demand mechanical isolation for thermal management.
Often, common heat sinking approaches can be used with SOP to minimize the number and handling of individual thermal solutions. Both direct lid attachment (DLA) and thermal paste solutions can be used when components are closely spaced; individual applications will require differing solutions.
1.4 Microvia and Wafer-Level Chip-Scale Package (WLCSP)
As mentioned earlier, CSP will have the largest percentage of CAGR in the future of IC packaging. WLCSP is not only one of the CSPs, but the real CSP. Also, WLCSP is considered potentially the most cost-effective and reliable package.
There are more than 30 different types of WLCSP reported in the literature, and their advantages and disadvantages have already been discussed. Just like many other new technologies, however, WLCSP still faces many critical issues (only solder-bumped WLCSP will be considered):
- The infrastructure of WLCSP is not well established.
- The standard of WLCSP is not well established.
- WLCSP expertise is not commonly available.
- Bare wafer is not commonly available.
- Bare wafer handling is delicate.
- The cost for poor-yield IC wafers is high.
- Waver bumping is still too costly.
- There is a high cost for low wafer-bumping yield, especially for high-cost dies.
- Wafer-level redistribution is still too costly.
- There is a high cost for low wafer-level redistribution yield, especially for high-cost dies.
- Troubles can occur with system makers if the die shrinks.
- Test at speed and burn-in at high temperature on a wafer are difficult.
- Single-point touch-up on the wafer is difficult.
- PCB assembly of WLCSP is difficult.
- Solder joint reliability is critical.
- Microvia build-up PCB affects WLCSP solder joint reliability.
- Alpha particle emission occurs through the lead-bearing solder on WLCSP.
- Lead-free solder regulations have an impact on WLCSP.
- Who should do the WLCSP? IC foundries or bump houses?
- What are the cost-effective and reliable WLCSPs and for what IC devices?
- How large is the WLCSP market?
- What is the life cycle of WLCSP?
One of the unique features of most WLCSPs is the use of a metal layer to redistribute the very fine-pitch peripheral-arrayed pads on the chip to much larger-pitch area-arrayed pads with much taller solder joints on the PCB or substrate, as shown in Figs. 1.2 through 1.5. Figure 1.2 shows the wafer-level redistribution. Figure 1.3 shows a cross section of the redistribution. Figure 1.4 shows a typical cross section of the WLCSP assembled on a PCB, and Fig. 1.5 shows the cross section of the WLCSP-PCB assembly in more detail. In this book a few new solder-bumped flip-chip WLCSPs will be discussed in Chap. 10. Also, solder developments for the next-generation high-density interconnects will be presented in Chap. 9.
In general, with LWCSPs, the underfill encapsulant may not be necessary (as shown in Fig. 1.4) and the demands on the PCB or substrate are relaxed. Since there is no underfill for most of the WLCSP assemblies, solder joint reliability becomes one of the most critical issues. Chapter 12 will address the solder joint reliability issues. A few new and high-throughput processes for assembling WLCSPs on PCB or substrate will be discussed in Chap. 11.
For solder-bumped flip chip on low-cost substrate or PCB applications, even with wafer-level pad redistribution (from peripheral array to area array) to relax the pressure on PCB or substrate, in many cases one to two or even three to four build-up layers with microvias are needed to fan out the circuitry. Chapters 3 through 7 will present, respectively, five different methods of forming the microvias, namely mechanical numerical control (NC) drilling, laser drilling, photo defining, etching, and conductive-material fill. A few very special and novel microvia build-up substrates for solder-bumped flip chip in packages are discussed in Chap. 8. Some necessary fundamental knowledge for making the conventional PCB or substrate is presented in Chap. 2.
FOR MORE INFORMATION
This material was excerpted with permission from Chapter 1, “Introduction to Microvia and WLCSP Technologies” in “Microvias For Low Cost, High Density Interconnects” by John H. Lau and S. W. Ricky Lee, Copyright 2002, The McGraw-Hill Companies, Inc, New York, NY