Solder has been the mainstream flip chip assembly method since the 1990s. Under-bump metallization (UBM) layers are deposited upon aluminum die bond pads at the wafer level.
Solder is dispensed by various methods onto the pads. Substrate pads are coated with solder flux and bumped die attached at elevated temperatures.
This established standard approach has proven suitable for many millions of flip chip assemblies, but it is not well-suited for today’s high-density electronics.
A common industry standard for solder bumping has been center-to-center spacing (pitch) of the bumps and pads of 150µm. Over the past few years, volume manufacturers have reduced pitches to below 100µm in production.
They are developing processes for 50µm pitch or less, challenging the limits of solder. (For reference, a human hair is 50µm to 100µm in diameter.)
An obvious solution is to eliminate solder, but unfortunately, replacements are not obvious. A promising method recently reported by Sandia National Laboratories is gold-to-gold bonding between thin layers (100 nanometers) of immersion gold.
The electroless nickel – immersion gold (ENIG) process announced in the 1990s, and its later development to include a layer of palladium (ENEPIG), are widely used for substrate metallization. They are maskless, low cost processes with proven reliability.
The Sandia objective is to develop flip chip bonding processes based upon bonding with the 100 nm immersion gold layers on ENIG/ENEPIG bumps.
This will allow direct gold-to-gold bonding of flip chip bumps to substrates with higher interconnect densities and at finer pitches than solder bump bonding can achieve.
Figure 1. ENEPIG Bump cross-section.
The experiments compared the bonding of gold stud bumps, ENIG bumps, and ENEPIG bumps to gold surfaces. A variety of surface preconditioning and bonding conditions (time, temperature, pressures) were compared.
- Gold Stud Bumps: an 8 X 8 array of gold stud bumps on a silicon die, made by ball bonding 25µm gold wire onto 100 µm square pads having 1µm gold coatings.
- ENIG/ENEPIG bumps: For either, 20 X 40 arrays of bumps on 400µm X 200µm x-y pitch on 150mm wafers. Aluminum pads, 100µm octagonal shape, with 80µm passivation openings.
- Nickel bump thicknesses of 5µm, 10µm, 15µm, 20µm, and 25µm nickel and 100nm gold. The ENEPIG bumps included a 0.35µm palladium layer beneath the gold.
FIGURE 2. Octagonal ENIG pads for array bumps.
- The bumped arrays were either bonded array-to-array or array to silicon substrates.
- Array bondings were ENIG to ENIG, ENEPIG to ENEPIG, or ENIG to ENEPIG.
- Substrate bondings were array to 10mm X 10mm silicon substrates.
- Substrate coatings were 1µm thick evaporated gold over 200nm titanium.
Gold surfaces of the test die were given one of three treatments:
- Coated with dodecanethiol self-assembling gold nanolayers (SAM)
- Argon plasma cleaned
- Cleaned in dilute piranha solution (deionized water, H2SO4, H2O2.)
- Finetech Lambda flip chip bonder
- Gold stud bump: 150 -155°C, 20N force, 30 – 45 seconds.
- Arrays: 185°C, 20N or 200N force, 20 – 30 minutes.
Gold stud bump bonding:
- Strong bonds, with average shear strength 1.2kg.
- Shear strength independent of surface pretreatment.
Arrays bonded to gold films:
- 185°C 25N force did not meet MIL-STD-883 die shear strength.
- 185°C 200N force formed acceptable bonds meeting MIL-STD-883 die shear strength.
- No improvement with SAM coatings, which showed large variations in shear strength not correlated to holding time before bonding.
Arrays bonded to arrays:
- Preliminary results show SAM treated arrays bond at 185°C, 200N force, 30 minutes.
These experiments demonstrated the suitability of ENIG and ENEPIG bumps for solderless flip chip bonding.
SAM coating the gold surfaces is advantageous compared to argon plasma cleaned gold surfaces because the storage time prior to bonding can be extended. Further work will compare surface pretreatments in more detail.
FOR MORE INFORMATION
Rohwer, L.E.S.; Dahwey Chu; Sandia Nat. Labs., Albuquerque, NM, USA “Thin gold to gold bonding for flip chip applications,” in ECTC 2011 IEEE 61st, pages 907 – 910.