Deborah Patterson, Amkor
This tutorial is based on the article: Transforming Mobile Electronics with Copper Pillar Interconnect
featured in the IMAPS Advancing Electronics (May/June 2012 issue).
The crux of today’s packaging innovations continue to be driven by silicon node reduction – and its corresponding die shrinks – coupled with increased functionality and higher bandwidth requirements. Applications processors and other logic devices are highly functioning SoCs with considerable signal I/O density. Along with the corresponding need for added memory and distinct operational features (such as sensors, cameras, etc.), new device integration schemes are forcing significant advances in IC packaging.
Smartphones and tablets comprise two of the fastest moving, highest volume, and most competitive markets in the world – with form, fit and function evolving at an unprecedented rate. Consequently, the necessity of managing costs, design complexity, and manufacturability results in continual innovation to meet the dynamic demands of the market.
A Healthy Market for Innovation
After the iPhone was introduced in June 2007 with its subsequent onslaught of device-specific applications, the idea of handheld “computing platforms” took a major step forward. Users reconsidered the types of functions that were necessary in a cell phone. The introduction of the iPad in January 2010 firmly established the tablet as a viable and exciting product. These types of mobile platforms now feed widespread use of media – and have facilitated an explosion in software development that has accelerated further demands on the device hardware (e.g., increased processing and functionality, decreased power and size).
The Trend Toward Finer Pitch Flip Chip (FPFC)
The mobile device market seeks a robust operating system, rich user interface, high processing performance, and resilient security. Equally desired is the ability to respond quickly to changing market conditions, to retain tight inventory control and rapid throughput, and to achieve high product yields. Each element must also be achieved without compromising the reliability or quality of the end product.
To address these requirements, fine pitch flip chip is replacing wire bonding in many higher end devices that require low profile and small area packaging. Within this category of devices, copper pillar bump technology offers several compelling advantages.
In 2005, wireless device suppliers adopted copper pillar interconnect in RF power amplifiers and front-end modules to obtain both performance and cost improvements. 1
In 2006, it was revealed that Intel had replaced its traditional SnPb flip chip solder bumps with a combination copper pillar/SnPb joint for their 65nm Yonah and Pressler processors. 2 The smaller bump form factor facilitated higher I/O densities. Prismark reported that Intel eventually migrated all of its products to Pb-free copper pillar interconnect technology. 3,4
Thinner Is Indeed Better – and Modularity Helps
Package-on-package (PoP) is a platform of choice for handheld electronics. PoP stacks are comprised of very low profile packages that combine independent logic and memory BGA packages stacked one on top of the other and leveraging a standard interface to route signals between them.
As fully assembled and tested stand-alone packages, PoP platforms provide modularization and form the building blocks of end-product differentiation. The PoP structures shown in Figure 1 illustrate the flexibility of the individual packages that are integrated into a single BGA platform, ready to be assembled onto a circuit board.
Figure 1. (a) Package-on-package (PoP) components illustrated on the top with a photo of the assembled structure below, and (b) Cross-sections illustrate a PSvfBGA or Package Stackable very thin fine pitch BGA (top), and a PSfcCSP or Package Stackable Flip Chip CSP (bottom).
In July 2010, Texas Instruments and Amkor announced the introduction of copper pillar flip chip packages in a PoP platform. The 45nm node applications processor required a 40/80 µm staggered bump pitch. Figure 2 shows a cross-section of the bottom package.5 The copper pillar bumps have a SnAg solder cap that joins to the copper trace on the BGA substrate.
Figure 2. (a) Cross-section of the TI XAM3715, a 45nm applications processor mounted on a BGA substrate, and (b) a close-up of the dual row staggered copper pillar bumps. (Source: Chipworks)
Figure 3(a) shows a SEM of 50µm in-line copper pillar bumps with SnAg solder caps. Fifty micron pitch copper pillar bumps are in high volume production today. When using copper pillar flip chip, 1-3 rows of staggered perimeter pitch bumps are typical. A SEM of 40µm area array bumps is shown in Figure 3(b) to illustrate bumping proficiency. These dense area array footprints are more complex than those found in handheld devices.
Figure 3. (a) SEM of 50µm in-line copper pillar bumps and (b) 40µm copper pillar area array (Source: Amkor Technology).
Fine Pitch Flip Chip (Copper Pillar) Package Options
The continued development from early flip chip in CSP, BGA and PoP platforms has spawned a broad selection of package types, all with the ability to integrate copper pillar interconnect. Figure 4 illustrates a selection of package configurations, from bare die on board to complex 2.5/3D through silicon via (TSV) designs, to provide a sense of the diversification of packaging options going forward.
Figure 4. Examples of package structures that can support fine pitch copper pillar flip chip.
Cost of Ownership Reduction and Performance Improvements
For mobile device manufacturers to differentiate themselves, design and manufacturing efficiencies must be delivered. These efficiencies may show up as a lower priced cell phone, or as a higher-end smartphone boasting more capability, longer battery life, and increased speed.
The drivers for placing fine pitch non-collapsible bumps directly on the final metal bond pads are numerous and include both performance improvements and cost of ownership reduction.
Traditional solder bumps used in the assembly of flip chip die are designed to collapse upon assembly, thereby providing self-alignment on the circuit board pad, accommodation of less than planar substrates, good wetability, and predictable failure modes as characterized by the chosen solder material. The limitation of solder-based flip chip joints has been one of pitch where the tightest pitches in mass production are on the order of 150µm, placing constraints on the overall I/O layout and the density of interconnections that can be achieved.
Given the factors identified in Table I and their widespread impact on profitability, ease of doing business, product performance and time-to-market, a concerted development program focusing on the manufacture and assembly of fine pitch copper pillar bumps was defined with materials development, equipment customization, and assembly processes investigated.
Table I. Benefits of Copper Pillar Bump-on-Pad and PoP Enabled Packaging
Developing the Assembly Process to Facilitate a Mobile Revolution
The identification, development and implementation of new materials and processes to address the structural considerations listed in Table I was challenging. Material qualification, equipment modification, and new process flows were created and compared to conventional flip chip assembly techniques with respect to cost, performance, reliability, throughput, etc.
The primary issues centered on developing processes (heating profile, bond force, etc.) that preserved the structural integrity of the very thin (≤100µm), fragile (low-K/ELK dielectric) die, the small copper pillar bump, and the SnAg solder joint. Each step in the die prep and assembly process had to yield a planar, rugged, and reliable structure that would pass JEDEC package and board level requirements. “Due to their extremely small size, these fine pitch interconnects are very fragile at the bump joint area [and] vulnerable to joint failure due to the stresses encountered during package and PWB assembly, created by the thermal mismatch between the die and the organic substrate.” 6
After an extensive investigation into the assembly processes to handle very thin, low-K die, the combination of thermo-compression bonding with non-conductive paste proved to be the optimal choice. It produced a viable, high volume assembly solution that preserved the integrity of the die, copper pillar interconnect, and substrate.
The process is illustrated in Figure 5. The non-conductive paste is applied to the substrate; the bumped device is aligned to within ≤5µm, and the underfill is snap cured. The most pressing challenge is the warpage that occurs between the thin die and the substrate. The snap cure process (a) reduces stress on the copper pillars, (b) reduces stress on the die, and (c) allows the substrate to maintain its planarity.
Figure 5. Process flow for thermo-compression bonding with non-conductive paste (TC-NCP) and resultant copper pillar bond.
Technology trends and consumer demand continue to dictate downstream packaging challenges. The considerable increase in I/O densities on today’s processors and ASICS (as a direct result of die shrinks and higher functionality) is primarily responsible for driving advanced interconnect and packaging development. The corresponding increase in signal I/Os have accelerated packaging complexity. The primary drivers are 7
- Form factor reduction for handheld devices coupled with
- Silicon node progression, both driving downstream assembly constraints,
- Higher power dissipation (where higher operating temperatures and increased current per bump generate more severe thermal management challenges),
- Higher operating frequencies and reduced noise margins,
- Increased use of application specific packages (e.g., sensors, MEMS, camera modules),
- Full conversion to green materials, and
- Relentless pricing pressure.
Copper pillar interconnect, along with innovative substrate, underfill, molding and assembly refinements provide for high I/O density, potential substrate cost reduction versus standard flip chip, improved electrical performance due to routing efficiencies, increased thermal conductivity and electromigration resistance. Copper pillar stacked packages enable a higher die to package area ratio ensuring minimum board real estate consumption along with the ability to take full advantage of the vertical space between the PCB and device enclosure.
Amkor has invested heavily in the development and expansion of high volume copper pillar bumping and TC+NCP assembly lines.
For further information on Amkor’s copper pillar flip chip capabilities click.
1 Lee Smith, “Copper Pillar Flip Chip Momentum is Accelerating,” Chip Scale Review Tech Monthly, March 2012.
2 Chipworks, “Intel D920 Presler and T2300 Yonah Copper Pillar Bump Technology Package Analyses,” April 3, 2006.
3 Prismark Partners, Semiconductor Packaging Report, Third Quarter Dec 2008.
4 Prismark Partners, Semiconductor Packaging Report, First Quarter May 2010.
5 Chipworks, “TI Ships 40-µm Fine Pitch Copper Pillar Flip Chip Packages,” October 4, 2010.
6 Lee, et al., “Study of Interconnection Process for Fine Pitch Flip Chip,” ECTC 2009.
7 Robert Darveaux, “Challenges & Solutions in Development of New Package & Interconnect Technologies,” SEMI Breakfast Forum, Tempe, AZ, October 2011.