Tutorial #38
Kimberley A. Olver
U.S. Army Research Laboratory
February 2004

INTRODUCTION

Indium bump technology is a unique process used mainly for flip chip assembly of semiconductor components. Some applications include bonding infrared detector arrays to multiplexers for focal plane arrays, GaSb quantum cascade lasers to thermally conductive mounts, and vertical cavity surface emitting lasers (VCSEL’s) to sapphire fanouts or driver electronics. Because of its cryogenic stability, thermal and electrical conductivity, self-adhesive (ductile) nature and relative ease of application, indium is a good material for these applications.

Indium is deposited onto a wafer as the last step in the photolithography/metalization process. A lift-off of the extra material produces pillars of indium several microns in height. Both components are processed with indium, and using a flip chip bonder, the parts are either compression or thermo-compression bonded together. Bump area determines the amount of pressure needed for successful bonding. If a substantial amount of indium is being used (e.g. for thermal conductivity) thermo-compression bonding will be necessary.

PROCESS OVERVIEW

Masks are designed for both top and bottom parts, and a thick photoresist is used so that several microns of material can be deposited. If commercial readouts are to be assembled, they should be purchased with indium bumps. For a 5 – 6 micron high indium pillar, an 8 – 9 micron thick photoresist layer is used. A vacuum-thermal evaporation of 300Å of chromium followed by several microns of indium is completed, a metal lift-off is done, and indium pillars (bumps) are the result. The height and shape of the bumps are determined by the photoresist used and the mask design.

Both the component and the readout are put into a flip chip bonder, the bumps are aligned in the x and y direction, planarity is established, rotation is corrected and pressure is applied. The amount of pressure being applied for a successful bond depends on the area of the bumps being brought together.

In some procedures, the indium is reflowed in an oxide-reducing atmosphere. Dome shaped indium bumps are created this way, and the process can be self-aligning. Both the top and bottom parts are reflowed, a rough indium bump alignment is performed, the indium is heated to its melting temperature, and the top and bottom indium bumps actually pull each other into place, finishing the alignment. The assembly is cooled to room temperature before removing from the flip-chip bonder.

Figure 1 shows the processing steps for evaporating indium bumps onto gold pads, which are further described below:

Gold pad on device – The device surface is cleaned using acetone and isopropyl, then dried with nitrogen.

Photoresist layer – A layer of thick photo resist is spun on to the surface of the device, and the specified photoresist baking is performed.

Photoresist exposure and develop – Using a chosen mask design, the photoresist is exposed and the indium bump pattern is developed. A plasma ash in an oxygen atmosphere cleans any undeveloped photoresist from the pattern openings prior to deposition.

Cr/In deposition – Using vacuum-thermal evaporation, 300Å of chromium, followed by 5 – 6 microns of indium are deposited. The chromium acts as a wetting metal for adhesion as well as a barrier metal between the gold pad and indium. Gold and indium form an intermetallic, and, above 125 C, this inter-metallic becomes brittle, compromising the integrity of the bonds. A 2:3 ratio of deposited indium height to photoresist thickness is typical for a successful lift-off.

Lift-off and cleaning – Lift-off is done by soaking the device in acetone (sometimes overnight). An airbrush and de-ionized water are used to remove the rest of the excess indium, leaving only the indium bumps.

RESULTS

Figure 2 and 3 are SEM images of deposited indium bumps.

Figure 2. 15mm x 22mm indium bumps on 30mm2 gold pads

Figure 3. A 20mm2 indium bump on a 40mm2 gold pad.

There are several advantages of indium bump bonding for hybridizing semiconductor devices to their counterpart readouts or driver electronics. Besides being inexpensive and relatively easy to work into a wafer-processing run, the technique has flexibility in the shape, size and placement of the bumps. Most of the time, the assembly can be performed with die at room temperature. This technique does not require flux. Newer, more sophisticated flip-chip bonders are able to perform wafer-to-wafer bonding utilizing indium bumps, which increases the throughput of devices being assembled.

Disadvantages include possible damage to the devices due to the compression required for assembly. Also, indium bumps are not easily reworked.

ACKNOWLEDGEMENTS

The author would like to thank Phillip Boyd of the Army Research Laboratory for his contribution of all SEM images.