Summarized from: “Next generation fine pitch Cu Pillar technology — Enabling next generation silicon nodes”,
presented at ECTC 2011, M. Gerber, C. Beddingfield, S. O’Connor (Texas Instruments);
Min Yoo; MinJae Lee; DaeByoung Kang; SungSu Park; C. Zwenger, R. Darveaux, R. Lanzone, KyungRok Park (Amkor Technology)
Increasing die complexities required by next generation mobile communications processors are driving the development of fine pitch copper pillar flip chip bump and assembly technologies. Amkor, working cooperatively with Texas Instruments, has introduced robust copper pillar flip chip bumping and assembly processes with bump pitches of less than 60um that meet these needs.
Fine Pitch Flip Chip Requirements
For mobile communications, flip chip development is driven by increased device performance and package miniaturization trends, particularly for the CPU or so called applications processor that powers smart phones and media tablets. Here, higher device performance leads to more input/output connections per IC, while miniaturization requires smaller/ thinner packaging, leading to smaller, closer spaced connections. Fine pitch flip chip reduces size while meeting the challenges of thinner ICs, fragile low-K dielectrics, and the need for tighter package warpage control to maintain robust IC and package reliability.
Smart phones and tablets drive the highest demand for flip chip based chip scale and 3D packaging technologies. Single die packages are most common, either as package-on-package (PoP) for logic plus memory stacking or as simple chip-scale packages (CSP). Stacked die packages are also used, where the applications processor is a fine pitch flip chip device with a wire bonded memory or modem IC mounted on top. Flip chip CSP or flip chip PoP may be molded or bare die, with variations in substrate layer counts, BGA pitches, IC thicknesses and sizes, bump counts and bump densities. Thus a broadly applicable, robust flip chip technology is required to address all of the possible configurations.
Copper Pillar Process Development
Test Vehicle Selection
Developing fine pitch copper pillar interconnect required selecting a test vehicle to prove out the baseline assembly technology and the robustness of the final package. Both the fine pitch copper pillar bump and the assembly process required new development, since the baseline technology was not available in the industry.
The qualification vehicle is important to understanding some pivotal process conditions. A Texas Instrument package with a 0.5mm pitch top interface memory pad array and a 0.4mm pitch bottom BGA array was selected. The overall package thickness was 0.82mm nominal and contained a bare flip chip die with 559 bumps at a 50um bump pitch.
This vehicle provided a popular flip chip PoP body size (generally 12mm or 14mm on a side) with a high enough bump count to support a wide range of target products. In addition, the bare die construction ensured that the proper die standoff height was achieved such that the top memory package was stackable in its final end-use application. In summary, a 12mm x 12mm fine pitch flip chip PoP test vehicle provided the ideal attributes to qualify a new fine pitch bump and assembly technology. The qualification vehicle’s package structure is shown in Figure 1.
Figure 1: Qualification test vehicle
A key objective in developing a low cost and robust fine pitch bump technology was to use both existing bump infrastructure and standard materials and process flows. Copper pillar can meet these key objectives. In addition, copper pillar bump
structures provide the low-stress interconnection required for advanced silicon node technologies.
Fine pitch copper pillar bumping is based upon the same process technologies currently used for the solder-plated bumping of today’s mainstream flip chip devices. Figure 2 illustrates the process flow for standard solder plated bumps.
Figure 2: Solder-plated bumping process flow
Current standard solder plated bumps require sputtering an Under Bump Metallurgy (UBM) across the silicon wafer. Photo imaging then forms openings in the photoresist that define the placement and size of the solder bumps. After the solder is plated within the openings, the defining photo resist is removed and the UBM that is not protected by the presence of a bump is etched away. The wafer undergoes a reflow and a cleaning process to form the final solder bump.”
The copper pillar bumping process flow is illustrated in Figure 3. Copper pillar bumps use the same thin film materials and processing techniques as conventional solder bumps, except that the copper is plated over the UBM, followed by plating a lead-free solder cap on top of the copper pillar.
Figure 3: Copper pillar bumping process flow
The copper bump structure before (left) and after reflow (right) is shown in Figure 4.
Figure 4: Copper pillar bumps
The design dimensions targeted for qualification are shown in Figure 5. Careful monitoring and control of the copper pillar’s critical features and physical properties is essential to ensuring a high quality, reliable bump structure.
Figure 5: Copper pillar bump structure
One key process optimization area for the copper pillar bump development centered on the UBM etch process and control. Figure 6 shows an example of a 50um copper pillar bump where copper residue was found during failure analysis. The failure showed up during electrical test as a short circuit. This potential fault triggered further characterization to ensure the bump process was robust.
Figure 6: Copper pillar UBM under-etch.
A bump shear test procedure was developed to ensure that the bump structures were robust and consistent across the entire wafer of each bumped lot. Shear failure modes were closely monitored to ensure strong, consistent bump structures. A weak interface can adversely affect the final flip chip interconnection quality. The desirable shear failure mode is a cohesive bulk failure within the plated copper structure. The undesirable mode is an adhesive failure at the UBM-to-copper interface, indicating a weak bond at this critical interface. These two types of failure modes are shown in Figure 7. Bump shear strength measurements after exposure to as many as 10 reflows ranged from roughly 15 to 17 grams.
Figure 7: Bump shear failure modes (Cohesive Copper Bulk & Adhesive UBM-to-Copper)
Besides monitoring the final bump structure’s attributes, such as critical physical dimensions and shear strength, in-process monitoring ensured a robust and reliable fine pitch interconnect technology. Once the process was fully characterized, Amkor’s copper pillar bump structure was available to support the development and qualification of Texas Instrument’s 12mm x 12mm fine pitch flip chip PoP qualification vehicle.
Copper Pillar & Flip Chip Assembly Process Development
Fine pitch flip chip devices introduce a number of new challenges throughout the assembly process flow. This drove the parallel development of both bump and assembly which helped to accelerate timely definition of the final process flows.
The primary process development challenge centered on the flip chip attach and bonding processes. For fine pitch copper pillar flip chip with pitches below 100um, the placement accuracy of the die to substrate is critical for high yield manufacturing. The material set and assembly technique must accommodate a wide range of die sizes and silicon thicknesses.
Early in the program, we interacted closely with strategic equipment and material suppliers to develop the best bonding process for high volume fine pitch manufacturing. An intensive technical capability assessment and cost of ownership analysis of all available flip chip bonding techniques concluded that thermal compression bonding was best suited for fine-pitch copper pillar products. Thermal compression bonding, used with a nonconductive paste (NCP), provided the most stable, scalable, and robust bonding technology for copper pillar bumping in support of next generation silicon node devices.
The thermal compression process flow is shown in Figure 8.
Figure 8: Thermal Compression Bonding Process Flow
High die placement accuracy is critical. Traditional solder flip chip pitches of 150-200um are not as stringent, since the reflow process will “self center” the die on the substrate. Conversely, fine-pitch copper pillar thermal compression bonding requires sophisticated pattern recognition and alignment compensation techniques to reach the very high alignment yield required for mass production. During the early stages of development, the team faced some key challenges to ensure the alignment during machine setup was adequate.
Figure 9 shows an X-ray view of a misaligned copper pillar bumps. Figure 10 shows perfect alignment.
Figure 9: Misaligned bumps.
Figure 10: Aligned bumps and cross-section
Another defect mode showed the importance of controlling the height of the die to the substrate, commonly called the bond line thickness (BLT). The BLT must be monitored to within a few microns to avoid squashing bumps. Figure 11 shows an example of an over-bonded copper pillar die where the solder cap can be seen migrating out the sides of the joint, causing solder shorts.
Figure 11: Over-bonding with solder migration.
Close monitoring of the critical setup height variables is important to reducing the chance of this problem. Pillar height, substrate capture pad height, and die thickness must be carefully controlled for a stable process.
We found that processing fine pitch copper pillar wafers required choosing backgrind tapes that would protect the formed copper pillars while ensuring good manufacturability. Figure 12 shows an example of an unformed joint because of an organic backgrind tape residue left on the copper pillar. The residue caused an open failure. A change in the tape material eliminated the problem.
Figure 12: Open Interconnect due to Backgrind Tape Residue
Prior to qualification, the assembly process was fully characterized to determine the process corners to ensure a repeatable and high quality process flow. The final assembly process flow is illustrated in Figure 13.
Figure 13: Cu pillar assembly process
Package Qualification Results
Standard JEDEC MSL L3 260ºC un-biased package reliability testing was performed to qualify the fine pitch copper pillar PoP devices. Three separate qualification lots were subjected to the un¬biased reliability testing. The qualification vehicle passed all the reliability tests per JEDEC MSL L3 260ºC requirements.
In addition to these non-biased component-level reliability tests, the qualification vehicle was subjected to board-level reliability (BLR) testing (drop and temperature cycle) and biased component-level reliability (CLR) testing. The qualification vehicle also passed all the read points per the JEDEC requirements.
During the development process, a number of bump and assembly process challenges were encountered and resolved. These included optimizing the UBM copper pillar etch conditions, eliminating any backgrind tape residue, avoiding squashed bumps, and optimizing die placement accuracy. A full set of reliability data was collected on the qualification vehicle. Both board level reliability and component level reliability testing was successfully completed.
The lead-free fine pitch copper pillar technology we developed is essential to assembling the next generation of semiconductor devices. Future semiconductor device challenges include higher pin counts, thinner die, higher performance requirements, and extremely low K dielectrics – all driving the need for a new packaging technology to address each of these challenges.
Gerber, M.; Beddingfield, C.; O’Connor, S.; Min Yoo; MinJae Lee; DaeByoung Kang; SungSu Park; Zwenger, C.; Darveaux, R.; Lanzone, R.; KyungRok Park; Texas Instruments Inc., Dallas, TX, USA; Amkor Technology Inc., Chandler, AZ, USA; Amkor Technology Korea, Seoul, Korea, “Next generation fine pitch Cu Pillar technology — Enabling next generation silicon nodes ,” in ECTC 2011 IEEE 61st, pages 612-618.
July 7, 2010 Amkor press release, www.amkor.com / Investors: “Amkor Technology and Texas Instruments Deliver Industry’s First Fine Pitch Copper Pillar Flip Chip Packages to Market” “New Packaging Platform Reduces Semiconductor Chip Size and Cost While Boosting Performance”
Minjae Lee; Min Yoo; Jihee Cho; Seungki Lee; Jaedong Kim; Choonheung Lee; Daebyoung Kang; Zwenger, C.; Lanzone, R.; Res. & Dev. Center, Amkor Technol. Korea Inc., Seoul, “Study of Interconnection Process for Fine Pitch Flip Chip,” in Electronic Components and Technology Conference, 2009. ECTC 2009. 59th , pages 720 – 723