Jan Vardaman and Linda Matthew, TechSearch International, Inc.
This tutorial is based on the article: Is There a Bump in Your Future? Growth of Flip Chip and Wafer Level Packaging
featured in the MEPTEC Report (Fall 2013 issue).
In the last decade, advanced packaging has emerged as an enabler of today’s electronic products. The impact of packaging, assembly, and test is increasingly felt in the semiconductor industry and the choice of the interconnect method is important in achieving device performance and form factor. Flip chip and wafer level packaging are expanding into a wide range of applications and device types as companies continue to move designs from wires to bumps.
Devices such as central processing units (CPUs), graphics processors (GPUs), Application Specific Integrated Circuits (ASIC), and other high-performance devices have been using flip chip in package (FCIP) for many years. FCIP is also expanding in mobile computing, especially smartphones and tablets. In units, the compound annual growth rate (CAGR) from 2011 to 2016 is almost 26 percent, while in number of wafers the CAGR is only 13.5 percent because much of the growth is for small size die such as filters found inside mobile device modules .
A History Lesson
While it has become a popular topic at conferences and in magazines, flip chip is not a new idea. Flip chip interconnect was introduced in the 1960s by IBM and the first version used a copper ball for its three terminal transistors called Solid Logic Transistor (SLT) . Flip chip was made famous with the introduction of IBM’s evaporation process called Controlled Collapse Chip Connection, often abbreviated as C4. Flip chip interconnect was also developed and used in products at Delco (now Delphi) and Denso in Japan for automotive applications, as well as Citizen Watch for watch modules. IBM’s technology was licensed to Motorola (now Freescale Semiconductor) and AMD. Intel had a cross licensing agreement and developed its own plating process. With the shift to large 300mm wafers, IBM and the rest of the industry moved from evaporation to plating. With the Pb-free movement, the industry adopted SnAg as the primary Pb-free solution of choice for plated bumps. Using current legal exemptions, some companies continue to ship products with eutectic and high-Pb solder bumps, but most companies have made the switch to Pb-free bumps. Today the industry is experiencing a transition from solder bump to copper pillar, just as it moved from an evaporated bump to a plated process.
Growth of Copper Pillar
Intel’s adoption of a copper pillar has helped to create the infrastructure just as Intel’s shift from ceramic to laminate technology provided the volume to develop the flip chip infrastructure enabling more widespread adoption of the technology. Intel started with the use of copper pillar in its 65nm and 45nm flip chip product lines, and is using copper pillar technology in its 32nm products. The first products were the “Presler” and “Yonah” processors, but today Intel uses the copper pillar process in all of its flip chip products . Cu pillar with a solder cap has also been used for GaAs and silicon in RF modules for several years. Amkor has been shipping RF Power Amplifier and RF front-end modules with Cu pillar bumps for many years. Drivers included size, performance, and cost. Copper pillar is also shipping in leadframe packages from companies including Amkor, ASE, Carsem, SPIL, and Unisem.
Cu pillar with mass reflow (source: Amkor Technology)
Copper pillar, post, or column as it is often called, is also expected to see greater demand as companies move to fine pitch solutions. There are many forms of copper pillar and a variety of applications. Some copper pillar examples are found in high-end processors and others are found in flip chip packages for wireless products. Copper pillar is also an option for micro bumps used for die attached to interposers and for die stacks. Xilinx’s highest performance Field Programmable Gate Arrays (FPGAs) use copper pillar interconnect for the die mounted onto a silicon interposer that is fabricated with TSVs in what Xilinx calls its “Stacked Silicon Interconnect” technology. Texas Instruments (TI) has adopted copper pillar technology in its application processor (OMAP) that is in the bottom package of the PoP . Amkor provides assembly services for this product and TI also has its own internal production line. Companies offering copper pillar bumping, include Amkor, ASE, Chipbond, FlipChip International, JCAP, NEPES, SPIL, STATS ChipPAC, TSMC and Unisem. GLOBALFOUNDRIES and others will offer copper pillar bumping in the next year.
With the variety of options come with a set of different material and equipment needs. With pitch trends below 100 microns, some companies are using a thermo-compression bonding process in which the flip chip die with is placed on the substrate, uses a non-conductive paste (NCP) underfill, and is bonded and the underfill cured at the same time . This is a departure from the conventional pick, place, and reflow oven process commonly used. Three types of underfill process and materials are used with copper pillar today: capillary, molded, and pre-applied. The best method depends on many factors including the application, bump pitch, and cost structure.
Wafer Level Packages
Wafer level packages (WLPs) are fully packaged before dicing and include bumped die that are not packaged or underfilled due to thermal stress management concerns. Typically the ball or bump is a larger diameter and has a larger pitch than those found in flip chip bump applications. While some WLPs use a printed bump, most versions use a preformed solder ball. Some WLPs such a MOSFETs make use of an electroless NiAu as the under bump metallization (UBM) with a thicker gold, a printed bump, or a preformed solder ball to achieve a low-cost structure.
Wafer with electroless NiAu UBM
(source: Pac Tech Packaging Technologies GmbH)
As end-users continue with the strong preference for small form factor, low profile consumer products, small packages such as WLPs meet the requirements. Demand for thin packages and greater functionality in smaller spaces drives the increased adoption of WLPs in mobile phones, especially smartphones and increasingly tablets. Many companies are designing wireless devices in WLPs, resulting in growth for 300mm wafers, but demand for 200mm wafers is also increasing.
Traditionally, WLPs were used for a variety of devices with low pin counts and small die sizes. WLPs are used for power MOSFETs, power management, controllers, ring tones for mobile phones, battery management devices, integrated passives, CMOS image sensors, diodes, EMI filters, and devices for ESD protection. Increasingly, larger devices such as integrated power management and wireless parts, such as RF components including Bluetooth and wireless LAN devices, are packaged in WLPs.
With increased interest in using WLPs for larger die with higher pin counts, an increasing number of companies are interested in using fan-out WLPs. Teramikros (formerly Casio Micronics) offers foundry services for WLPs using its copper post and the technology has been used for many years in mobile phones and consumer products such as watches. Infineon’s wireless division (now owned by Intel) developed a “molded reconfigured wafer” technology for its fan-out WLP solution called eWLB. The chip backside and edges are covered with a mold compound and array interconnect solder balls are attached to the active side of the die. This allows the use of fan-out redistribution. The technology is targeted at medium to high I/O count (<300) devices such as baseband processors and multiband transceivers . Several companies have licensed Infineon’s eWLB technology, including ASE, NANIUM, and STATS ChipPAC, and production lines have been installed. TSMC has also announced its own fan-out WLP.
WLPs offer a small footprint and a low-profile solution that enables ultrathin consumer products such as smartphones and tablets. The CAGR for WLPs in units from 2011 to 2017 is almost 13 percent for the six-year period, while the CAGR in wafers is slightly over 14 percent. While many wire bond designs are transitioning to WLP, some FCIP is also converting to WLP. Analog devices account for large shipment numbers in both units and wafers, but shipments of devices with RF functions are also contributing to strong growth.
Flip chip and wafer level packaging continues to expand to a wide range of applications and device types. Drivers for flip chip continue to be performance and form factor. Increased demand for thinner, lighter-weight portable products continues to WLP growth. For many companies, a bump will increasingly be in their future.
(1) E. J. Vardaman, Linda C. Matthew, and Laurie S. Roth, “2013 Flip Chip and WLP: Recent Developments and Market Forecasts”, TechSearch International, March 2013.
(2) Peter Elenius, “A Short History of Flip Chip and Wafer Level Packaging,” Advancing Microelectronics, January/February 2013, pp. 6-8.
(3) A. Yeoh, et al., “Copper Die Bumps (First Level Interconnect) and Low-k Dielectrics in 65nm High Volume Manufacturing, 2006 Electronic Components and Technology Conference, May 2006, pp. 1,611-1,615.
(4) M. Gerber, et al., “Next Generation Fine Pitch Cu Pillar Technology—Enabling Next Generation Silicon Nodes,” 2011 Electronic Components and Technology Conference, May 31-June 3, 2011, pp. 612-618.
(5) Hamid Eslampour, et al., “fcCuBE Technology: A Pathway to Advanced Si-node and Fine Pitch Flip Chip,” 2012 Electronic Components and Technology Conference, May 29-June 31, 2012, pp. 904-909.
(6) T. Meyer, et al., “eWLB System in Package Possibilities and Requirements,” International Wafer Level Packaging Conference, October 11-14, 2010, pp. 160-166.
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