Tutorial #4
Richard Estes
January 2001

Introduction to Polymer Flip Chip

A reliable and manufacturable flip chip infrastructure continues to develop worldwide. Significant advances in equipment, processes for flip chip interconnect, and long term reliability of the flip chip assemblies are causing a shift from chip and wire interconnect to non-packaged direct chip attach.

Miniaturized packages, higher density electronics and higher speed are the motivating forces for the true chip size, low inductance electrical interconnection that flip chip offers. As shown in Table 1, the ability to form a high input-output (I/O) packaging concept with low contact resistance, low capacitance, and low lead inductance will drive the microelectronics industry conversion from chip and wire to flip chip.

Flip chip interconnect technology will become the ultimate surface mount (SMT) technique in the 21st century, replacing BGA, μBGA, and CSP, which are best categorized as transition packages. All of these will use flip chip for electrically attaching the integrated circuit (IC) to the package substrate, until cost and space needs require eliminating the package altogether.

The three basic technologies underlying most of the hundreds of flip chip interconnect techniques are anisotropic materials, metallic bump technology, and isotropic conductive polymers. The process and reliability information which follows here focuses on the isotropic conductive polymer approach, or P_FC® process. This process uses silver (Ag) filled thermoset and thermoplastic polymers, in combination with stencil printing processes, to form polymer bump interconnects for flip chip integrated circuit (IC) devices.

The following discussion of under-bump metallization (UBM) over aluminum, bump formation processes, and overall reliability of flip chip devices compares the relative performance of the thermoset and thermoplastic polymers which form the primary electrical interconnection.

Polymer Bump Interconnect Processes (P_FC®)

Overview
The P_FC® process is a patented, stencil printing technology in which isotropically conductive, silver filled polymers are stencil printed through metal stencils to form polymer bumps on the UBM which covers the aluminum bond pads of I.C. devices. The sequential techniques to achieve polymer bump interconnections are UBM, polymer stencil printing for bump formation, flip chip attach to effect the electrical connections and underfill for enhanced mechanical and environmental integrity. When all processes have been optimized for a particular application, the result is a true chip-size, flip chip interconnection providing a highly reliable electrical interconnect technology.

Under Bump Metallization (UBM)
As with virtually all flip chip processes, the aluminum bond pads must be re-metallized to eliminate non-conductive aluminum oxide. This insures a low and stable contact resistance at the “bump-bond pad” interface. The polymer flip chip process uses zincate-nickel gold electroless plating. The resulting nickel-gold metallization layer averages 3.0-5.0 microns thickness. The P_FC® process yields bumps with less than 10 milliohms resistance, adequate for most applications where high speed is required.

Polymer Flip Chip: The P_FC® Process
The polymer flip chip process combines high precision stencil printing techniques with highly conductive, isotropic, conductive polymers. The polymers are either thermoset, which cures with heat, or thermoplastic, which softens with heat. These silver-filled polymers are formulated for high precision stencil printing through laser etched or electroformed metal stencils. Table 2 describes the three types of bumps that are formed by the stencil printing processes.

TABLE 2

Once the bumped wafers are diced, the chips are inverted and bonded to the substrate. Final processing involves a heat cure for the thermoset bumps while the thermoplastic bump connections are made in a few seconds as heat and pressure are used to melt the thermoplastic. An underfill is then injected into the cavity between chip and substrate to complete the flip chip process. The function of this encapsulant is to provide mechanical integrity and environmental protection the flip chip assembly.

Bump heights are typically 50 to 75 microns and the process accommodates center-to-center spacings of 125 microns. The process works well for peripheral pad layouts, staggered patterns, or full arrays created through bond pad redistribution. The bump patterns are formed by the deposition of the thermoset or thermoplastic through the metal mask directly onto the metallized bond pads. Bump densities of up to 80,000 bumps/wafer have been formed with excellent co-planarity of the bump array.

Thermoset and Thermoplastic Comparison
The decision to use thermoset polymer bumps or thermoplastic bumps depends on the application as previously stated. The thermoplastic bump process for polymer bump interconnects requires one less process step than thermoset, offers reworkability, and has a low elastic modulus, important where thermal expansion (CTE) mismatch is of concern. The thermoset process is well suited for higher temperature applications, where thermoplastic melt temperatures are too low, or for applications requiring low temperature processing, where thermoplastic melt temperatures are too high. Processing on PVC, for example, requires a thermoset polymer that cures at 75°C.

Table 3 compares thermoset epoxies and thermoplastic polymers used in the P_FC® process. Both polymers consist of long polymer chains, with silver flake filler providing conductivity, and a rheology suitable for stencil printing of bumps as small as 70 microns in diameter.

The following discussion on reliability includes “application specific” case studies where the overall reliability of flip chip assemblies is summarized and the relative performance of thermoset versus thermoplastic polymer bump interconnects is documented.

Silicon to FR4 Test Vehicle
A 40 I/O, silicon to FR4 test vehicle was created for evaluating both thermoset and thermoplastic polymer bump interconnects. The metallization was gold on both chip and FR4 and the thermoset and thermoplastic polymers were stencil printed onto silicon wafers. Bond pad diameter was 125 microns and pitch was 250 microns. In this study the EPO-TEK E2101 (thermoset) and EPO-TEK K5022-115BE (thermoplastic) were used to create the bumps for interconnect.

Flip chip assemblies were made with both thermoset and thermoplastic adhesive and these were subjected to various environmental tests. Initial resistance values were in the range of 10 milliohms/bump. The change in resistance was monitored and reported after testing. Tables 4 gives the relative performance of thermoset and thermoplastic bumps used in flip chip assembly. Resistance values are in milliohms. All assemblies were underfilled with U300.

TABLE 4A: E2101 Thermoset Adhesive

TABLE 4B: K2022-115BE Thermoplastic Adhesive

The data suggest no catastrophic failures such as bump delamination or cracks as resistance values do not shift significantly, nor are any opens reported. The E2101 resistance values show less increase, especially in thermal shock and pressure cooker testing. This may be because the E2101 thermoset bumps adhered better to the gold surfaces or because the higher Tg of the thermoset bump resulted in better dimensional stability of the flip chip connection.

Overall, however, there is no substantial difference in the performance of thermoset and thermoplastic bumps. The data suggests that both types of polymers offer reliable flip chip electrical interconnections.

Outlook for Polymer Flip Chip

The production and performance of a widening range of microelectronics devices for industrial and consumer applications can benefit from the use of flip chip as opposed to wire connection assembly. When conductive polymers are used instead of solder for flip chip electrical interconnection and bonding, significant advantages are seen in processing cost and efficiency, and in the electrical, thermal, and mechanical performance of devices. Polymer flip chip is a low temperature process that facilitates high volume production and component miniaturization.

FOR FURTHER INFORMATION

You may reach Mr. Richard Estes through email: rhestes@earthlink.net