Higher density 3D with direct die-to-die interconnection has been a major industry goal for the past decade. As transistors shrink towards horizontal scaling limits, growing vertically is an attractive alternative.
Direct local die to die vertical connection of internal circuit elements with heterogeneous integration and repartitioning is the final goal. 3D local interconnection offers shorter signal paths, higher speed, higher volumetric efficiency, lower power consumption, and lower cost.
Wire bonded memory die stacks have long been available. Interconnections are to ordinary input/output (I/O) pads, which are global interconnects rather than local. These indirect signal paths slow transmission and waste power. Often the wires are the greatest source of power dissipation.
Through-silicon vias (TSVs) are conductive columns connecting vertically through a die from one side to the other.
Basic TSVs are well proven. TSVs are already used in CMOS imagers and MEMS arrays.
More than 50 companies have been involved in developing high density 3D. Fifteen different 300 mm 3D-IC pilot production lines are reported to be currently operating or being installed.
Yole Développement recently forecasted that the market for 3D integration using TSVs will grow from slightly less than $500 million in 2010 to over $4 billion in 2015, a compounded annual growth rate of 52%. 
As fine pitch TSVs move towards pilot production, the current technical challenge is how to best handle, stack, and bond thinned TSV die and wafers.
A collection of leading-edge technical papers recently compiled and released as a free Technical Bulletin by SET S.A.S. gives a sample of the wide variety of 3D approaches that different companies are developing. 
For example, the papers show that:
- CEA/Leti-MINATEC prefers direct die bonding without polymer layers, to produce a thinner die stack with lower thermal strain and wider post-processing limits. 
- IMEC uses tacky dielectric layers to hold many precisely placed die for simultaneous bonding. 
- IMEC has also developed a sequential die stacking process where adding subsequent die does not disturb the lower stack. 
- RTI International finds that Cu/CuSn bonding will compensate better for surface irregularities, but Cu/Cu bonding yields stronger bonds than Cu/CuSn, a major benefit with differing thermal expansion coefficients in heterogeneous die stacks. 
- Most developers fill TSVs from the top side down, but ITRI reports that bottom-up filling has cost and throughput advantages. 
- IME-A*STAR reports using electroless nickel-immersion gold (ENIG) to cap high-aspect-ratio TSVs for solder bonding. 
Much early 3D work concentrated on wafer to wafer (W2W) bonding, which has a throughput advantage in simultaneously bonding all devices on the wafer. Bonding die one-by-one to a wafer is very time-consuming. However, recent advances in die-to-wafer (D2W) bonding now allow all die to be placed or even stacked sequentially onto the wafer, before simultaneously bonding all of them.
D2W assembly has many advantages. Separately mounting only known-good die onto the wafer allows connecting them only to known good wafer die, raising final yields. D2W assembly readily accommodates heterogeneous mixes of die, including unequal die sizes and thicknesses within a stack; W2W does not.
Single die are quickly aligned and placed over typical distances of a few millimeters, while 300 mm W2W alignments are slower and risk more problems from wafer flatness deviations and from thermal expansion.
Timely availability of advanced equipment has been a key enabler of 3D development. Advanced bonders for 3D must accommodate the wide range of process parameters demanded by competing companies trying to establish their own proprietary process flows.
3D/TSV technical problems now being addressed include developing common design tools, implementing standards, establishing supply chains, handling thermal hot spots, and demonstrating long-term reliability.
Simply adding 3D elements to today’s 2D designs will not maximize the benefits of 3D. Taking advantage of features such as direct local die to die connection and repartitioning requires a system redesign with new tools.
Heterogeneous die stacking will require integrating die from different manufacturers. Standards will be needed to ensure common interfaces among die from different suppliers. Just as JEDEC standards today specify pin-out locations, 3D standards will be needed tomorrow to specify “via-out” locations.
A major supply chain question is where in the production line will TSVs be created – as part of wafer fabrication, or at the end, as part of packaging? The answer affects both via processes and via locations.
It also determines who in the supply chain does the job, wafer suppliers or packaging houses. Much current opinion favors middle-of-line over front-end or back-end approaches.
Thermal control raises performance and reliability issues. While die stacks have many advantages, heat dissipation is not one of them. In today’s 2D layouts, a die can use an exposed back side for cooling or heat sinking.
Within a stack, neither side of a die may be available, and local hot spots could occur. Liquid cooling, carbon nanotube heat sinks, and thermal vias are among the possible thermal options.
- Industrialization of high density TSVs continues on course.
- Technical problems remaining to be solved include design, standards, supply chain, thermal, and reliability. Design systems and standardization will appear when commercial needs are clearly established.
- Some among the many development processes may converge, but both the diversity of goals and the competitive drive for proprietary processes make a single, “one-size-fits-all” process unlikely.
- Equipment suppliers currently assisting commercialization will develop more specialized equipment as the needs become clear
- Cooperative efforts of equipment suppliers and research/development teams should carry high-density TSV-based 3D into volume production over the next five years, as forecasted by Yole.
 “SET is well Positioned and Prepared to address the Challenges of the Fast Growing 3D System Integration Market”, J-M. Yannou, Yole Développement.
 Technical Bulletin, “Die Bonding Applications,” SET S.A.S., Saint-Jeoire, France, January 2010. See below for more information.
 “An Innovative Die to Wafer 3D Integration Scheme: Die to Wafer Oxide or Copper Direct Bonding with Planarised Oxide Inter-Die Filling”, L. Di Cioccioa, P. Gueguena, L. Claveliera, T. Signamarcheixa, L. Ballya, L. Vandrouxa, M. Zussya, S. Verruna, J. Dechampa, P. Leduca, M. Assousa, D. Bouchua, F. de Crecya, L-L. Chapelonb*, R. Taibib*, CEA/Leti-Minatec, *STMicroelectronics, IEEE 3DIC 2009.
 “Electrically Yielding Collective Hybrid Bonding for 3D Stacking of ICs”, A. Jourdain, P. Soussan, B. Swinnen, E. Beyne, IMEC, ECTC 2009.
 “High Density Cu-Sn TLP Bonding for 3D Integration”, R. Agarwal, W. Zhang, P. Limaye, W. Ruythooren, IMEC, ECTC 2009.
 “High Density Cu-Cu Interconnect Bonding for 3-D Integration”, J. Lannon Jr., C. Gregory, M. Lueck, A. Huffman, D. Temple, RTI International, ECTC 2009.
 “3d Stacked Chip Technology Using Bottom-up Electroplated TSVs,” H.H.Chang, Y. C. Shih, Z. C. Hsiao, C. W. Chiang, Y. H. Chen, and K. N. Chiang , Industrial Technology Research Institute (ITRI), ECTC 2009.
 “Study of 15µm Pitch Solder Microbumps for 3D-IC Integration”, A. Yu, J. H. Lau** , S. Wee Ho, A. Kumar, W. Yin Hnin, D-Q. Yu, M. Ching Jong, V. Kripesh, D. Pinjala, D-L. Kwong, Institute of Microelectronics-A*STAR,
** Department of Mechanical Engineering-Hong Kong University Science & Technology, ECTC 2009.