Hua Ye,Cemal Basaran, and Douglas C. Hopkins
Based upon the paper:
Mechanical Implications of High Current Densities in Flip Chip Solder Joints
Hua Ye,Cemal Basaran, and Douglas C. Hopkins
UB Electronic Packaging Laboratory,University at Buffalo
SUNY, Buffalo, NY 14260 www.packaging.buffalo.edu
We studied the electromigration damage to flip-chip solder joints of eutectic Sn/Pb under current stressing at room temperature with a current density of 1.3x104A/cm2. The mass accumulation near the anode side and the void nucleation near the cathode were observed during current stressing.
In the preliminary experiment, the surface marker movement technique was used to measure the atomic flux driven by electromigration and to calculate the product of effective charge number and diffusivity (DxZ*) of the solder.
Subsequent experiments revealed that joule heating caused significant thermomigration. This makes the extraction of the product of effective charge number and diffusivity erroneous when using marker movement technique.
The trend in flip-chip and ball grid array (BGA) packaging is to increase input-output (I/O) count. This trend drives the interconnecting solder joints to be smaller in size and, thus, they have a higher current density. The current densities further increase as chip voltage decreases and as the absolute current level increases.
There is also a similar drive in flip-chip power semiconductors and evolving system-on-package power processors to increase the current densities [1;2]. A physical limit to increasing current density in both microelectronics and power electronics is electromigration. Electromigration of interconnecting metal lines is the major source of failure in integrated circuits, but it is seldom recognized as a reliability concern for solder joints. Most of the published literature on electromigration focuses on thin, pure metal lines, and there is little published on present-day solder interconnects [3-7].
This work covers the electromigration damage to eutectic Sn/Pb flip-chip solder joints under current stressing of 1.3x104A/cm2 at room temperature ambient. The test flip-chip modules were produced in an industrial lab to obtain consistent interconnects representative of high volume commercial manufacturing.
The test module has a dummy silicon die with only an aluminum (Al) conductor trace on it. The silicon die is attached to a FR4 printed circuit board (PCB) through eutectic Pb37/Sn63 solder joints. The copper plates on the PCB provide the wetting surface and the electric connection to the solder joints. The under bump metallization (UBM) on the silicon die side is electroless nickel (ENIG). The voids between the solder joints are filled with underfill between the silicon die and PCB substrate.
The thickness of the Al trace is about 1 mm and the width is about 150 mm. The diameter of the solder joint is around 140~150 mm and the height is about 100 mm. The test module was cross-sectioned and finely polished towards the center of the solder joints before current stressing.
Two solder joints were tested on each module. The solder joints on each test module are configured so that current always flows from the copper trace through solder joint A into the Al trace on the silicon die, and then flows through solder joint B out to another copper trace. Figure 1(a) shows the schematic cross section of the test module and the direction of current flow in the experiments.
In the preliminary experiment, only solder joint A was measured. However, interesting results were revealed by measuring both solder joint A and B on the test module in subsequent experiments. Mass accumulation near the anode and void nucleation near the cathode were observed during current stressing in Module #1. Lead (Pb) phase coarsening was also observed during the experiment.
We used surface marker movement to measure the atomic flux driven by electromigration and to calculate the product of effective charge number and diffusivity (DxZ*) of the solder. Subsequent experiments revealed that thermomigration due to joule heating makes the extraction of the product of effective charge number and the diffusivity results flawed.
Figure 1. (a) Schematic cross-section of the test module (b) SEM secondary image of solder joint on module #3
The eutectic Sn/Pb solder joints on Module #1 were cross-sectioned and polished for direct observation of electromigration. Figure 1 shows a schematic cross-section of the solder joint and a SEM secondary image of the cross section. The joint was subjected to current stressing with 1 Amp DC at room temperature, yielding an average current density through the solder joint of 1.3×104 A/cm2 based on its diameter. We removed the test module for scanning electron microscopy (SEM) analysis after 3, 6, 14.5, and 37.5 hours of stressing. A nano-indentation experiment was performed on the solder joints of Module # 1 after 37.5 hours of stressing.
Figure 2 shows the SEM backscattered images of the cross-sectioned surface of the solder joint for zero and 37.5 hours of current stressing. SEM secondary images of the joint after 37.5 hours of stressing are shown in Figure 3 at several magnifications. The SEM backscattered image gives more information about elemental composition, whereas the secondary image gives more topographic information .
Figure 2. SEM backscattered image of solder joint on Module #1 for (a) initial, and (d) 37.5 hrs
The direction of electron flow is from the Ni UBM on the silicon die side to the Cu plate on the printed circuit board side. The mass accumulation on the anode side and the void nucleation on the cathode side can be seen in Figure 2 and Figure 3. The surface of the cross-sectioned solder joint became very rough due to electromigration after 37.5 hours. Large depressed areas formed on the cathode side and large voids formed near the Ni UBM side. This indicates large amount of mass depletion in the region.
Figure 3. SEM secondary images for Module #1 (a) after 37.5 hours, magnification 700x (b) Area on the PCB board side (anode), 2000x; (b) Area on the silicon die side (cathode), 2000x.
Hillocks formed near the Cu plate region due to mass accumulation. Hillocks and crystalline formation were clearly shown in the anode region in Figure 3(a). Figure 3(c) clearly shows both voids and cracks near the cathode region.
Thermomigration due to the thermal gradient (which is caused by joule heating) within the flip-chip solder joint is significant and may be a leading cause of diffusion [10;11]. In our subsequent experiment, the microstructural evolutions of solder joints A and B of a test module are measured during current stressing. The temperature on the silicon die is measured with a fine-tipped thermocouple thermometer. The measurement indicated that the temperature at the surface of the silicon die of 100~150ºC was much higher than ambient temperature. This conflicts with the initial assumption that the die surface temperature was close to the ambient temperature .
In a typical flip-chip module, the cross-section area of the metal trace on the silicon die is much smaller than that of the solder joint. Therefore, the primary heat source is the metal traces, which contribute most of the electric resistance of the module. The joule heating during current stressing maintains a thermal gradient within the solder joint.
This is verified by the 3-dimensional coupled thermal-electrical finite element simulation of the real structure of the flip-chip test module [10;11]. The temperature of the simulation is in agreement with the temperature measured on the silicon die and indicates that a temperature gradient as high as 1,500ºC/cm may be maintained within the solder joint. The temperature at the silicon die/solder interface is much higher than that on solder/copper plate interface [10;11]. This thermal gradient is well beyond the reported thermal gradient needed to trigger thermomigration in solder joint .
The main goal of this project was to identify the mechanism of electromigration damage in microelectronics solder joints.
Experiments revealed that, when joule heating raised the die surface temperature to 100 – 150 C, thermomigration became significant compared to electromigration. Thermomigration at that level makes the extraction of electromigration data using the marker movement technique erroneous. Advanced thermal management may be required to obtain electromigration data with the marker movement technique. The temperature gradient within the solder joint must be small enough to make thermomigration negligible compared to electromigration.
This project is sponsored by the U.S. Office of Naval Research Advanced Electrical Power Systems program under Mr. Terry Ericsen and by International Microelectronics and Packaging Society (IMPAS). We gratefully acknowledge all the help we received from Dr. Darrel Frear and Dr. Jong-Kai Lin of Motorola, Inc. in Tempe, AZ who provided all the flip-chip test vehicles.