Tutorial 1 , “Introduction to Flip Chip,” posted October 1, 2000, presented a brief summary of flip chip basics. This update celebrates the new decade and the one-hundredth tutorial in this series with a look at flip chip progress since 2000. I will follow and update the original section headings, while linking to related later tutorials.
WHAT IS A FLIP CHIP?
My 2001 definition of flip chip microelectronic assembly “the direct electrical connection of face-down electronic components onto substrates, circuit boards, or carriers” must now be enlarged to include electro-mechanical (MEMS), electro-optical, and bio-sensor components. These components now may be mounted onto flexible circuits, wafers, and other chips, such as memory, processors, sensor arrays, or 3D die stacks.
WHY USE FLIP CHIP?
The principal benefits of flip chip remain unchanged: smallest size, highest performance, greatest I/O flexibility, most rugged, and lowest cost. All benefits may not be simultaneously available — for example, smallest size and highest performance may conflict with lowest cost – but the benefits have been proven and even extended by the many new materials, methods, and equipments used to produce flip chips.
HOW IS FLIP CHIP MADE?
The three basic steps remain: bumping, attaching, and (generally) underfilling with an electrically non-conductive adhesive.
In 2001, I included “solder bump” as a single material category, since most solder bumped flip chip then were the eutectic tin-lead solder used for centuries. Other solders now include eutectic gold-tin, better for higher temperature performance and for reduced creep in optoelectronic devices. Indium solder (Tutorial 38) allows self-welding bumps for large focal plane arrays, and has superior low-temperature performance for chilled detectors.
The 2003 political decision by the European Union to eliminate lead solders in 2006 (Tutorial 66) led to an assortment of potential lead-free solders, with varying degrees of acceptance. The most common are various formulations of tin, silver, and copper, e.g. SAC305, composed of tin (Sn) with 3% silver(Ag) and 0.5% copper (Cu). Several second-generation lead-free replacements are being developed to remedy first-generation defects.
Solder alternatives in the 2001 tutorial included conductive adhesives. Anisotropic film adhesives (ACF) then were principally for connections to flat panel displays. ACF and its relatives have since flourished in high-volume applications such smart cards, cellular phones, and other consumer products (Tutorial 96). Non-conductive adhesives are another solder alternative, creating metal-to-metal connections without requiring a separate underfill step.
Plated gold bumps and gold stud bumps continue to be used for all-gold applications. Faster stud bumping equipment (Tutorial 50) and higher bump count thermosonic bonding has made stud bump more common for gold to gold connections.
Bumps have changed shapes and sizes, as well as materials. Copper columns capped with solder, nickel, gold or indium now give a higher aspect ratio, higher shear strength, higher conductivity, and a better match to copper on-chip metallization (Tutorial 28). The lower limit of fine bump pitch has progressed from the 100 µm range to below 10 µm in leading-edge 3D assemblies. Large focal plane imaging arrays now exceed 4 million bumped vertical connections per chip.
Solder deposition methods listed in 2001 – evaporation, electroplating, screen printing, needle depositing – now include solder spheres, jetting, and injection molding. Multi-component solder alloys may be dispensed as ‘pre-mixed” spheres. An advantage is easily matching three-component compositions of lead-free solder. Newer solder deposition methods include jetting of melted solder onto pads (Tutorial 61), or distributing melted solder into a mold with cavities patterned to match all of the solder pads on an entire wafer (Tutorial 56). Again, exotic compositions are readily accommodated.
Capillary and needle-dispensed underfills have been augmented with precision jet dispensing (Tutorial 76). In addition, pre-dispensed underfills or flux/underfill combinations speed up processing, as do faster-curing underfills.
Clearly flip chip has grown up, becoming better known and more widely used. An estimated 22 million wafers will be bumped in 2010. New approaches have opened many new applications. Nanotechnologies are beginning to demonstrate applications in flip chip, from high thermal conductivity bumps (Tutorial 60) to improved solder pastes (Tutorial 80). The new decade will see more merging of nanotechnology and microelectronics in what might be called micro-nano flip chip.Top ^