Tutorial #126, Part 2 of 2
Deb Kaller / Parallel Semiconductor, LLC
Multi-chip package solutions have many potential benefits, including footprint shrink, improved performance, reduced time to market, and reduced cost. Part 1 of this tutorial covered system types, package size analysis, thermal considerations and performance/die design factors. This second part will cover cost considerations and flexibility. The engineers may not find cost-centered topics as interesting as the technology topics, but historically cost has been the reason for slow uptake of multichip package solutions, such as multi-chip modules (MCM’s) from the early 1990’s, processor and memory stacks using wire bond technology in the early 2000’s, and thru-silicon via’s (TSV) today.
In any multi-chip package, the goal is to have die that yield well at test so that good chips and packages are not scrapped because one die was bad. A multi-chip package is much more sensitive to die test yield than a multi-package system. The following equation can be used to calculate the cost adder (to each good unit produced) resulting from yield loss:
- Yield cost = (component cost / compound yield) – component cost
(Component cost is the sum of the package cost plus the cost of each die)
(Compound yield is the product of the final (test) yield of each die and the package)
For example, if you had a system where the package cost $1, three die that each cost $5, a package yield of 100%, and final test yield for each die of 98%, the yield cost would be:
- Yield cost = [($1 + $5 + $5 + $5) / (1 * 0.98 * 0.98 * 0.98)] – ($1 + $5 + $5 + $5) = $1.00
The following figure illustrates the cost sensitivity to yield loss. Observe that if the dies are yielding 80% each, the yield cost is more than the component cost. If the alternative was to package each die separately into a $0.33 package, the yield cost of each packaged die would only be $0.11 (or $0.33 for all three). By doing the multi-chip package, the yield cost more than triples.
To prevent this yield loss, additional test circuits can be added to each die and additional testing can be done at probe to improve the final test yield. For memory, more redundancy can be added. However, this does not come for free, as die size or test time will increase. Also, overkill of good die can result from overly tight probe test limits. In some cases, there will be further challenges to test since full functionality cannot be tested until the die is mated with other die in the system. In the case of die normally packaged in wafer scale packages, probe testing is not usually even done since all the die on the wafer have to be packaged anyway.
For embedded die technologies, substrate yield must be taken into account, because a good die goes into each substrate whether it works or not. Yields below 90% are not uncommon for advanced substrate technologies with dense routing. casose devicesalog), a lower cost process node may bthe subsystemogy for devices which are
In the case of large systems, there is a die yield benefit by using multiple chips. Wafers will have a certain number of processing defects, independent of die size. As the die get larger, die yield decreases as shown in this simple graphic (1):
An example of using multichip technology to support extraordinary transistor counts — the Xilinx FPGA, where 4 chips with a total of 6.8 billion transistors are placed on a silicon TSV interposer (2, 3).
There are further costs specific to multi-chip products beyond the cost factors already mentioned (package technology cost, die size, design costs, yield).
Cost improvements over SOC are possible by using multiple fabrication technologies, each matched to the function of the subsystem. This can reduce the number of lithography layers on the silicon, and reduce device size by using the optimum fab process. An example of this is putting control functions for memory on a logic process, and just memory cells on the memory chips. This is the structure used for the Hybrid Memory Cubes (4). For subsystems with devices which don’t scale well (such as analog), a lower cost process node may be used.
In the case where die are purchased, margin stacking (the need for two companies to get margin on a die) needs to be evaluated. The company that makes the bare die needs to get their margin (and the general rule of thumb is that bare die will cost as much as a packaged die, if not more). The company that buys this chip and assembles it into a multi-chip solution also needs some margin even if they don’t expect to “make” money on this chip, as there are overhead costs associated with design of the system, inventory, reliability testing, and customer quality. OEM’s who sell their own chips likely don’t have a model for the margin needed to break even, and customers are reluctant to pay for any added margin. This is especially a problem with memory when the customer (such as a large cell phone manufacture) gets very good pricing on memory. Help from the finance group is usually needed to determine this cost.
Inventory cost of a purchased chip is higher than a chip manufactured internally, as the value of a purchased chip is based on price, rather than the lower valuation that accounts just for the cost of materials and labor. Inventory cost of memory is even more costly, because memory prices drop over time.
When going into an area of new technology with either the package or die design, there are risks that can result in cost adders. Effort should be made to understand the current status of the technology, such as reliability results and production levels, with careful examination of how close the development work (or current production) is to the proposed product. Maturity of the supply line should be assessed, as well as any partnership agreements with assembly or die suppliers. These risks should be aligned to the risk tolerance of the new product.
One further cost factor is royalties. Many of the technologies used for multichip products are new and well patented, and require paying licensing fees. If using an offshore assembly house, they likely bundle licensing into their cost (and their licenses may prohibit them from saying how much they pay).
One last factor to consider when looking at a multichip product is ability to make changes to the chips. Changes may be necessary to accommodate customer needs, such as a different memory density or functionality. One of the benefits of a multichip product is flexibility (mix and match) without needing to spin a large SOC. Often, not all of the scenarios are available at the start of design, and what seems like a small change to die size or pin-out can run into a design rule boundary which is not easily overcome.
Another need for flexibility is lithography changes that make a qualified chip either unavailable or expensive. For example, memory changes lithography every 12 – 18 months. Carefully review the product design and qualification cycles, as it is possible that the memory will be obsolete just after qualification is complete. Further, memory often changes aspect ratio: one generation of a given density is square, in the next generation the same density will be rectangular (and smaller). This can mean a die that fits nicely in one generation doesn’t fit at all the next.
click here for Part 1
Deb Kaller founded Parallel Semiconductor LLC in 2007 with a focus on integrated circuit package technology development and intellectual property management for the handheld and portable markets.