Tutorial #126, Part 1
Deb Kaller / Parallel Semiconductor, LLC
Multi-chip package solutions have many potential benefits, including footprint shrink, improved performance, reduced time to market, and reduced cost.
System Integration / Source: Georgia Tech (1) click to enlarge
Recent developments in flip chip technology, such as 3D thru-silicon via (TSV) stacking, no-flow underfill (NUF), and embedded die technologies have enabled more and better multi-chip product options. The new technologies are exciting and hold much promise, but factors beyond just the package technology need to be considered. The aim of this tutorial is to provide insight into the many parameters to be analyzed when looking at a multi-chip solution. Part 1 of this tutorial will cover system types, package size analysis, thermal considerations and performance/die design factors. Part 2 will cover yield and other costs, plus the needs and limits on flexibility of systems.
Several technologies support 2D side-by-side arrangement of die. Traditional organic flip chip substrates support 2D solutions; new developments in no-flow underfills, copper pillar interconnect, and advanced substrate technologies make very dense systems with close die to die spacing possible. In fan-out wafer level packages (FO-WLP), also known as embedded wafer level ball grid array (eWLB), reconstituted wafers provide the ability to put 2 or more chips together. Older technologies including ceramic and silicon substrates have long supported multi-chip modules (MCM’s), now thru-vias in silicon or glass allow much higher interconnect density, with more direct signal paths to a motherboard.
Examples of 2D systems:
2D flip chip / Source: Microsemi (2)
2-chip eWLP / Source: Insights From Leading Edge (3)
New technologies using flip chip interconnect for 3D stacked arrangement of die are becoming production worthy. Thru-silicon via (TSV) stacking technology has the potential for vastly improved product performance by enabling very short interconnects between chips, as well as significant package size reduction, especially for memory. Another technology for 3D packaging is die embedded into organic substrates, resulting in efficient combination of large and small die. Older 3D technologies include face-to-face flip chip interconnect with a wire bond connection to the substrate, as well as flip chip of die to both the top and bottom of a substrate.
Example of a 3D system:
Hybrid memory cube / Source: Computer World (3)
Further combinations can be made of the above technologies – such as substrate embedded die with multiple chips attached to the substrate top, or TSV with side-by-side die on one level of the stack.
There are several factors that need to be considered when estimating the package size in side-by-side solutions. Die size is key: not just the total area, but the geometry. For example, if combining a large square die with a small square die, the small die can result in substantial additional package area over a single die system-on-chip (SOC) solution, whereas combining two rectangular die will not result in a package size penalty. Keep-out zones between the die as well as between the die edge and package edge add to the total package area, and will vary considerably depending on the substrate type, attach process, and underfill used. Substrate routing can become more complicated, moving from symmetrical layouts for a single die to tangled interconnects between die. This can result in either a larger package size or a more advanced substrate technology. When new technologies are used, design rules should be scrutinized to determine what has been successfully used in production. A common issue with new geometries, such as rectangular shapes or thinner die, is warpage.
The package size may increase due to ball (I/O) count resulting from added functionality, conversely, if the die to die interconnects (such as a memory interface) eliminates package pins the package size can be smaller. Stacking die seems an obvious choice to reduce package size over a 2-D solution, but routing complexity and ball (I/O) count can limit the reduction. If mixed wirebond and flip chip technologies are used, there is an added penalty of keep-out zones, as you cannot wirebond close to underfill.
A benefit of most multi-chip solutions is lower power, due to short interconnects with less resistance, capacitance, and impedance. The power drop between two chips can be less than the power drop of a long interconnect run on thin on-die metal; for example the die to die interconnect for TSV is only 10’s of microns versus 100’s of microns. Even in a side-by-side example, use of a thick copper interconnect on a substrate can have lower resistance than on-die metal. However, as more functionality is squeezed into a smaller area, heat removal becomes challenging. Even though the total power may be less, the thermal dissipation paths need to be evaluated. One (often overlooked) thermal problem is mixed die technologies, as different technology types have different temperature limits. Memory presents a special challenge when combined with a microprocessor, as processor die typically have a maximum junction temperature (Tjmax) of 125oC, but memory die are typically limited to a Tjmax of 85 to 95oC. In a TSV stack, there is virtually no temperature drop between the hot spot on the processor and the memory die that is stacked on it. In RF modules, some power devices can run with a junction temperatures as high as 150oC, but if nearby passive components have strong temperature coefficients, the circuit will not perform as desired.
In order to get better performance by integrating multiple die into a package, new circuit architecture is needed. For example, when combining a microprocessor and memory die in a TSV stacked configuration, the microprocessor needs to directly access the memory die in get maximum performance. The die must be co-designed from very start of architecture definition, resulting in long lead-times. In cases where existing die will be used, pad positions may need to be optimized with a redistribution layer (RDL) to allow routing on the substrate technology of choice. Other considerations for design are the availably of design tools which are compatible over multiple silicon and circuit technologies (possibly at multiple companies), and the ability to handle new interconnect technologies. If the dies are being designed by different companies, a close partnership is needed through-out the design process.
To achieve optimum package size, x vs. y dimensions need to be considered as rectangular die shapes are often more desirable, but this can increase the “non-active” die area at the edges of the chip typically used for I/O. Chip to chip interconnects will add to I/O area in comparison to a system-on-chip (SOC) solution. Of special concern is I/O count so high in relation to the active die area that the design is pad limited, will result in un-used silicon area. Any time that two die are interconnected, it is desirable to use I/O structures which do not have the typical ESD protection to reduce impedance in the system. This has a benefit of reducing the I/O cell size.
Power delivery to the chips can be challenging in some multichip configurations. In a TSV stack, the power to the top chip(s) needs to pass through the bottom chip, which will take up valuable die area. Suitability of power and ground planes should also be evaluated, as die maybe far away from the ground plane, or complex routing on the substrate can compromise the planes by needing excessive via holes.
Multi-chip solutions often have unique design for test challenges. Wafer probe tests can be problematic because key functionality may not be present without its “partner” die. Lack of ESD structures results in pads that cannot be conventionally probed. Another issue is trouble- shooting the fully assembled package when direct access to memory or other key subsystems are not available.
Part 2 covers yield and other costs, plus the needs and limits on flexibility of systems.
Deb Kaller founded Parallel Semiconductor LLC in 2007 with a focus on integrated circuit package technology development and intellectual property management for the handheld and portable markets.