George A. Riley
A new method for determining the quality of flip chip bumps has been demonstrated by MultiMetrixs. Their feasibility study shows that their Resonance Sensor Technology (RST), already proven in wafer and thin film inspection equipment, could be the basis for a high-speed wafer bump inspection and test machine.
The RST approach applies electrical resonance techniques to provide extremely sensitive measurements of bump to wafer contact quality. The results include indications of both bump mechanical adhesion and electrical connectivity.
The feasibility demonstration was performed with a manual, single bump inspection probe. A standard pogo-pin served as the sensor head/probe, providing 100 kHz AC electrical signals to each bump, while making simultaneous resistance and capacitance measurements. A microscope with XY stage motion allowed visual alignment of the probe and test bumps. Test chips included good bumps and known bad bumps.
RST probing shows that each bump has a unique electronic AC resistance and capacitance signature. A die with good adhesion shows high conductivity that varies from bump to bump because of the logic structure, interconnections, and design of the die. A good adhesion bump also shows relatively high capacitance.
Bumps with poor adhesion or poor electrical connectivity show significantly lower conductivity and capacitance. Bump capacitance between good and bad bumps varies by 80% or more. Ninety percent of capacitance variations among good bumps are less than 10%.
Bump adhesion testing is necessary but not sufficient for determining bump quality. For example, a bump that is removed and glued back, or that has oxidation or chemical residues between the underbump metal and the bump could show good adhesion but poor or no electrical connectivity. The RST combination of simultaneous resistance and capacitance testing determines both the mechanical and electrical quality of the connection.
Figures 1 through 3 show a comparison of capacitance measurement plots from three identical bumped die. Each position on each plot represents a capacitance measurement from one bump. While dies 2 and 3 have relatively consistent capacitance measurements, die 1 shows significantly different measurements from the other two, indicating bump problems. Simultaneous resistance measurements of the three die showed similar variations.
Figure 1. Bump resonance capacitance plot, die 1.
Figure 2. Bump capacitance plot, die 2. Note differences from die 1.
Figure 3. Bump capacitance plot, die 3. Note similarity to die 2.
MultiMetrixs has plans for follow-on development of an automated 200mm/300mm wafer bump tester. Extending the pogo-pins in a linear array or an XY matrix would allow high speed testing of bumped wafers. The machine would have an estimated throughput of 15 or more wafers per hour with 225,000 bumps per wafer. The tool could also have other uses, such as UBM and die logic evaluation. MultiMetrixs is currently seeking corporate partners to work with them on development of the new machine.
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