Tutorial #91
George Riley
February 2009

NOTE: Details of the C4NP process and its advantages for lead-free solder bumping may be found in Tutorial 55, Tutorial 56, and Tutorial 63.

IBM has been in production with injection-molded C4NP solder bumping for two years. Meanwhile, IBM research continues to improve the process, shrink feature sizes, and move towards new applications.

Process improvements that IBM is developing include fine-tuning the solder bump transfer from the mold to the wafer. Increasing solder protrusion from the mold during transfer improves pad wetting. Solder centering in the mold is being tweaked, to enhance pad to bump alignment.

Mold to wafer compliance is being addressed for better transfer of solder to the wafer. A flexible mold may be part of that solution. Feature size limits are being driven towards 5 microns. “Partial bumps” are being considered to reduce 3d stacking height.

IBM qualified 50 micron bump diameters more than a year ago. Now IBM has 50 micron bump pitches, with potential contact densities of 104 to 105 connections per square centimeter. Figure 1 shows a portion of a wafer bumped with lead-free bumps at 50 micron pitch.

Nine million molded bumps were transferred from the mold to the wafer. This fine-pitch capability has been proven on both 200mm and 300mm wafers. The higher packing efficiency of the microbumps both reduces cost and shortens inter-chip distances for higher performance.

Figure 1. Lead-free solder bumps on 50 micron pitch.

In a new application, IBM has created silicon package integration with C4NP microbumps connecting multiple die face-down on silicon interposers. The interposer has multi-layer wiring and through-silicon vias (TSV). This approach accommodates both heterogeneous die and integrated passive devices. Since the die contain no TSV, creating the integrated silicon package requires only normal back-end tooling.

Figure 2 shows a silicon package assembly for power devices, with the back side of the die available for cooling. An early target application is power amplifiers in Wi-Fi and cellular chips.

Figure 2. Integrated silicon packaging.

In another application, small microbumps are big advantages in die stacking. Figure 3 shows a 4-layer stack of die connected with microbumps. The stack be assembled sequentially, placing and reflowing one die at a time, or the entire stack can be simultaneously reflowed to avoid multiple re-heating.

Figure 3. Four stacked die.

While these assemblies depend on small bumps, a new IBM application of IMS is also literally a large opportunity. The same general injection-molding process, with a deeper mold, has created a column-grid array on substrates through injection-molding columns instead of bumps. Figure 4 shows a substrate with injection- molded columns 2.3 mm high.

Figure 4. Injection-molded column grid array.

Finally, IMS (the “parent” technology of C4NP) has also recently demonstrated bumping capabilities for organic laminate substrates that address the decreasing bump size and pitch limitations using solder paste screening or ball mount. More details will be forthcoming at this summer’s ECTC conference in San Diego.

In summary, C4NP is not only fulfilling its promise for lead-free bumping,it is expanding – and contracting – injection molding’s space to serve broader applications.

FOR MORE INFORMATION

An IBM presentation on 3D C4NP, as well as more about C4NP in general, can be found on the site of their C4NP partner company, SUSS MicroTec, at www.suss.com/products/c4np

All graphics in this tutorial are courtesy of IBM.